Semiconductor Device Multi-Mode Burn-In Testing
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Solution Overview
Problem
Current semiconductor device testing methods, such as burn-in tests, require significant time to accurately estimate the lifetime of semiconductor devices and sort out weak devices, necessitating a more efficient testing approach.
Innovation Solution
A semiconductor system and method that utilize a controller and semiconductor device with multiple test modes, activated by specific combinations of burn-in test signals, clock signals, and command/address signals, allowing for efficient execution of different test operations, including stress application and data storage, to reduce testing time and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a burn-in test is performed to accurately estimate the lifetime of semiconductor devices, then the reliability of the test result is improved, but the test time required increases significantly
Solution Approach 1:
The burn-in test is divided into multiple test modes (first test mode, second test mode, third test mode) that can be executed sequentially or selectively. Each test mode focuses on specific aspects of device reliability, allowing comprehensive lifetime estimation without requiring the full duration of a traditional burn-in test. The test controller selectively activates different test modes based on device characteristics and test requirements.
Solution Approach 2:
The patent implements preliminary stress application and device characterization through the first test mode before proceeding to more time-consuming evaluation phases. By pre-screening devices and applying initial stresses, the system identifies weak devices early, reducing the overall test time required for accurate lifetime estimation of surviving devices.
2Adaptability or versatility
If multiple test modes are implemented to evaluate different aspects of device performance, then the comprehensiveness of testing is improved, but the device complexity increases
Solution Approach 1:
The test controller is designed as a multi-functional unit that can execute different test modes (first test mode with write operations, second test mode with read operations, third test mode with stress application) using a unified control architecture. This universal controller handles various test scenarios without requiring separate dedicated circuits for each test mode, thereby reducing overall device complexity while maintaining comprehensive test coverage.
Solution Approach 2:
The patent implements dynamic test mode selection where the test controller adaptively switches between different test modes based on device responses and test progression. The test controller dynamically adjusts operation voltages, clock frequencies, and test parameters during execution, allowing comprehensive evaluation without requiring static, overly complex circuit designs for all possible test scenarios simultaneously.
Data Source
AI summary
A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.