Semiconductor Device Multi-OS Descriptor Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with multiple processors executing different operating systems, the processing load increases with the amount and frequency of data communication, particularly due to the need for inter-OS communication and descriptor management, leading to inefficiencies and potential performance bottlenecks.
Innovation Solution
A semiconductor device architecture is implemented with separate descriptor and data areas for each operating system, where one processor controls a shared communication circuit by transferring communication instruction information between these areas, reducing the need for frequent data copying and interrupt handling, thereby alleviating processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processors share one communication circuit through inter-OS communication, then security is maintained, but processing load increases with data amount and communication frequency
Solution Approach 1:
The patent copies communication instruction information from the second descriptor area to the first descriptor area. Instead of transferring actual data through the communication circuit, only the control information (descriptors) is copied between memory areas, significantly reducing the processing load while maintaining secure shared access to the communication circuit
Solution Approach 2:
The first processor acts as an intermediary that manages communication circuit access for multiple OSs. The first descriptor area serves as an intermediary memory structure that stores communication instructions for both OSs, allowing the communication circuit to be shared without increasing processing load
2Speed
If descriptor type DMA transfer is used for data transfer, then data transfer speed is improved, but processing complexity increases due to descriptor management requirements
Solution Approach 1:
The patent merges the management of communication instructions for multiple OSs into a single unified descriptor area structure. By combining descriptor management for both first and second OSs in the first descriptor area, the system maintains DMA transfer speed while simplifying the overall processing complexity through centralized control
Data Source
AI summary
The memory includes a first descriptor area and a first data area corresponding to the first OS, and a second descriptor area and a second data area corresponding to the second OS. The second processor stores the first transmission instruction information corresponding to the transmission data stored in the second data area in the second descriptor area and transmits a first update notification of the second descriptor area to the first processor. In response to the first update notification, the first processor reads the first transmission instruction information stored in the second descriptor area and stores the first transmission instruction information in the first descriptor area. The communication circuit controlled by the first processor performs transmission process of transmission data stored in the second data area based on the first transmission instruction information stored in the first descriptor area.