Semiconductor Memory Multi-Bit Writing With Data-Based Verify Voltage
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Solution Overview
Problem
Existing semiconductor memory devices require unacceptably long times for writing and reading multi-bit data due to the need for multiple write operations and lengthy verification processes.
Innovation Solution
A semiconductor memory device with a control circuit that performs multi-bit-data writing in two steps, including a first programming of one memory cell, reading of data from that cell, a second programming of an adjacent cell, and verification based on the read data, with a verify voltage set on the second word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is written by performing write operations multiple times, then data storage capacity is improved, but writing time becomes unacceptably long
Solution Approach 1:
The write operation is segmented into two distinct phases: a first write operation that programs the first memory cell, and a second write operation that programs the second memory cell. This segmentation allows the operations to be performed in an optimized sequence rather than requiring multiple complete write cycles, thereby reducing total writing time while maintaining multi-bit storage capacity.
Solution Approach 2:
The first write operation is performed as a preliminary action before the second write operation. By programming the first memory cell first and using its read data to determine verification voltage for the second cell, the system prepares necessary information in advance, enabling the second write operation to proceed more efficiently without requiring additional verification cycles.
2Quantity of substance
If multi-bit data is written by performing write operations multiple times, then data storage capacity is improved, but reading time becomes unacceptably long
Solution Approach 1:
The first memory cell is programmed and read in advance before the second write operation commences. This preliminary reading provides verification data that is used to determine the appropriate verification voltage for the second memory cell, thereby streamlining the subsequent read operation and reducing total reading time.
Solution Approach 2:
The read data from the first memory cell serves as feedback to determine the verification voltage applied during the second write operation. This feedback mechanism ensures that the second cell is programmed with appropriate verification parameters, reducing the need for iterative verification cycles and thereby reducing reading time.
3Device complexity
If verification is performed with fixed verification voltage, then process simplicity is maintained, but writing precision deteriorates due to data retention deterioration
Solution Approach 1:
The verification voltage is made dynamic rather than fixed. The verification voltage for the second memory cell is determined based on the read data from the first memory cell, allowing the system to adapt verification parameters to actual data conditions. This dynamic adjustment compensates for data retention deterioration and improves writing precision without significantly increasing process complexity.
Solution Approach 2:
The verification voltage parameter is changed based on the state of the first memory cell. By adjusting the verification voltage according to the read data (e.g., applying different voltages for different data patterns), the system compensates for data retention effects and ensures accurate programming of the second memory cell, thereby improving writing precision.
Data Source
AI summary
A semiconductor memory device includes a memory string and a control circuit. The memory string includes a first memory cell connected to a first word line and a second memory cell adjacent to the first memory cell and connected to a second word line. The control circuit is configured to perform a multi-bit-data writing with respect to each of the first and second memory cells. The multi-bit-data writing includes, in order, a first programming to program the first memory cell, the first programming with respect to the second memory cell, a reading of first data from the first memory cell, a second programming to program the second memory cell, and a verification of data programmed in the second memory cell. The control circuit is configured to set a verify voltage to be applied to the second word line during the verification based on the first data.