Semiconductor Device Multichip Integration Wiring Reduction
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Solution Overview
Problem
Existing semiconductor devices with multichip module structures require larger mounting areas due to the size disparity between semiconductor chips and wiring boards, leading to increased wiring length and reduced signal processing speed.
Innovation Solution
A semiconductor device design where the first semiconductor chip is opposed to the second semiconductor chip with a connection member, an insulation film, rewiring layer, and external connection terminals, allowing for reduced wiring length and higher density integration, enabling faster operation and smaller mounting area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wiring board is used to mount semiconductor chips, then electrical connection between chips is achieved, but the device size becomes larger than the chips themselves
Solution Approach 1:
The patent extracts and eliminates the wiring board from the device structure. Instead of mounting chips on a separate wiring board, the chips are directly bonded to each other through connection members, removing the unnecessary substrate that increased device size while maintaining electrical connectivity.
Solution Approach 2:
The patent merges the functions of the wiring board and the chip mounting substrate into a single integrated structure. The chips are directly mounted on a chip mounting substrate that also provides the electrical connection function, eliminating the need for a separate wiring board and reducing overall device size.
2Reliability
If a wiring board with bonding wires is used to connect semiconductor chips, then electrical connection is established, but the wiring length increases
Solution Approach 1:
The patent removes the bonding wires and wiring board from the structure, replacing them with direct chip-to-chip connection members. This eliminates the long wiring paths that extended from the chips through the wiring board, significantly reducing the overall wiring length and improving signal integrity.
3Area of stationary object
If the device size is reduced to match chip size, then mounting area is minimized, but wiring complexity increases
Solution Approach 1:
The patent combines the electrical connection function directly into the chip mounting structure. Connection members are formed as part of the chip bonding process itself, integrating the wiring function into the mounting substrate and eliminating separate wiring layers, thereby reducing device complexity while achieving compact size.
Data Source
AI summary
A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.