Semiconductor Device Multilayer Dummy Pattern Alignment

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Solution Overview

Problem

Semiconductor devices with MRAMs face issues of short circuits between adjacent bit lines due to random placement of dummy patterns in the peripheral region, leading to uneven polishing of interlayer insulation films and potential failures in miniaturized devices.

Innovation Solution

A semiconductor device design featuring a multilayer structure in the peripheral circuit region, composed of layers matching those of the magnetoresistive elements, which overlaps second wires but not adjacent pairs, ensuring proper alignment and preventing short circuits, thereby achieving uniform interlayer insulation film thickness and flatness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy patterns are formed in the peripheral region to improve polishing uniformity, then the flatness of interlayer insulation film is improved, but short circuits between adjacent bit lines may occur due to random placement of dummy patterns

Engineering Contradiction:

Improveflatness of interlayer insulation filmVSAvoidshort circuit prevention

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The dummy patterns are strategically positioned to overlap only with second wires (bit lines) and not with adjacent pairs of second wires. This localized quality control ensures that polishing uniformity is improved in regions where dummies are placed, while avoiding the creation of short circuits between adjacent bit lines by excluding areas where dummies would bridge adjacent wires.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The peripheral region is segmented into specific zones where dummy patterns can be placed without causing short circuits. By dividing the region and assigning specific functions to different zones (overlapping with single wires vs. avoiding adjacent wire pairs), the design achieves both polishing uniformity and electrical isolation.

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If dummy patterns are placed to overlap adjacent pairs of second wires, then polishing uniformity is improved, but short circuits between adjacent bit lines occur

Engineering Contradiction:

Improveuniformity of interlayer insulation film thicknessVSAvoidshort circuit between adjacent bit lines

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The invention converts the potential harm of dummy patterns causing short circuits into a benefit by strategically positioning them to overlap with second wires for polishing uniformity while explicitly avoiding overlap with adjacent pairs. The constraint that prevents short circuits becomes the guiding principle for optimal dummy placement, turning a design limitation into a structured solution.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If coupling wires are used to connect storage elements and bit lines, then electrical connection is achieved, but device complexity and production cost increase

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidnumber of coupling wires and fabrication steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts and eliminates the need for separate coupling wires by designing the dummy patterns to serve dual purposes: maintaining polishing uniformity and providing electrical connection pathways. The dummy structures themselves become the connection medium, removing the need for additional coupling wire layers and reducing overall device complexity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The dummy patterns are designed to perform multiple functions simultaneously: they maintain interlayer insulation film uniformity during polishing, serve as electrical connection pathways between storage elements and bit lines, and avoid creating short circuits. This multi-functionality eliminates the need for separate coupling wire structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8686392B2Semiconductor device

Publication Date: 2014.04.01 RENESAS ELECTRONICS CORP

AI summary

The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.