Semiconductor Device Multilevel Data Storage Circuit
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Solution Overview
Problem
Existing semiconductor devices require a large number of power supply potentials to write multilevel data, leading to complex circuit configurations.
Innovation Solution
A semiconductor device comprising a transistor, switches, and capacitors, where the capacitance values are optimized to allow multilevel data writing and reading with a small number of power supply potentials, using oxide semiconductor switches to reduce leakage current and enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of power supply potentials are used to write multilevel data, then the data storage capacity is improved, but the circuit configuration becomes complex
Solution Approach 1:
The patent divides the data storage function into multiple capacitors (first capacitor, second capacitor, third capacitor) that can be independently controlled. Each capacitor stores a portion of the multilevel data, allowing the system to achieve high storage capacity without requiring a proportional increase in power supply potentials. The segmentation of storage elements enables complex data representation with simpler control signals.
Solution Approach 2:
The patent employs preliminary action by pre-charging capacitors to specific potentials before data writing operations. The first capacitor is charged to a first potential, the second capacitor to a second potential, and the third capacitor to a third potential in advance. This preliminary charging state enables multilevel data to be written using only two power supply potentials (first and second potentials) rather than requiring multiple potentials corresponding to each data level.
2Device complexity
If the number of power supply potentials is reduced, then the circuit configuration is simplified, but the ability to write multilevel data is compromised
Solution Approach 1:
The patent transitions from a one-dimensional approach (using multiple power supply potentials to represent different data levels) to a multi-dimensional approach by introducing multiple capacitors that can be independently charged to different potentials. With three capacitors each capable of holding one of two potentials, the system achieves 3-bit (8-level) data storage using only two power supply potentials, effectively adding dimensional complexity to the storage mechanism while reducing control signal complexity.
Solution Approach 2:
The patent employs preliminary action by pre-charging capacitors to specific potentials before data writing operations. The first capacitor is charged to a first potential, the second capacitor to a second potential, and the third capacitor to a third potential in advance. This preliminary charging state enables multilevel data to be written using only two power supply potentials (first and second potentials) rather than requiring multiple potentials corresponding to each data level.
3Reliability
If oxide semiconductor switches are used, then leakage current is reduced and data retention is improved, but manufacturing complexity may increase
Solution Approach 1:
The patent applies parameter changes by utilizing oxide semiconductor material properties to achieve extremely low off-state current (less than 1×10^-21 A/μm at room temperature). This material parameter change enables the switches to maintain stable charged states in capacitors over extended periods, providing excellent data retention. The oxide semiconductor switches (first switch, second switch, third switch) control the charging and discharging of capacitors with minimal leakage, ensuring data integrity without requiring additional error correction circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies circuit configuration by reducing the number of power supply potentials needed, enabling efficient multilevel data writing and reading while maintaining data integrity over time.
Implementation Method 1
a first terminal of the capacitor is electrically connected to a gate of the transistor. A first potential is supplied to the gate of the transistor through the first switch. A second potential is supplied to a second terminal of the capacitor through the second switch.
Implementation Method 2
The first and second switches are preferably transistors each including an oxide semiconductor in a channel formation region
Data Source
AI summary
The semiconductor device includes a transistor, first to N-th switches (N is a natural number of three or more), and first to (N−1)-th capacitors. A first terminal of the first capacitor (or a J-th capacitor) is electrically connected to a gate of the transistor (or a second terminal of a (J−1)-th capacitor (J is a natural number of two or more and (N−1) or less)). A first (or K-th) potential is supplied to the gate of the transistor through the first switch (or a second terminal of a (K−1)-th capacitor through a K-th switch (K is a natural number of two or more and N or less)). A capacitance value of the first capacitor is preferably equal to a gate capacitance value of the transistor, and a capacitance value of the J-th capacitor is preferably equal to a capacitance value of the (J−1)-th capacitor.