Semiconductor Multilevel Receiver Clock Phase Adjustment
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Solution Overview
Problem
Existing semiconductor devices and memory systems face challenges in accurately restoring multilevel signals due to improper phase adjustment of clock signals, leading to errors in data transmission and reception.
Innovation Solution
A semiconductor device is designed with a multilevel receiver and a clock generator that adjusts the phase of the clock signal based on the occurrence probability of invalid signals, ensuring accurate restoration of multilevel signals to data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase of the clock signal is not properly adjusted, then the multilevel receiver cannot accurately restore multilevel signals, but adjusting the phase requires complex control mechanisms
Solution Approach 1:
The patent implements a feedback mechanism where the multilevel receiver monitors the restored data signals and generates control information indicating whether restoration is accurate. This control information is fed back to the clock generator, which automatically adjusts the clock signal phase based on the feedback. This closed-loop feedback system eliminates the need for complex manual phase adjustment mechanisms while ensuring accurate signal restoration.
Solution Approach 2:
The clock generator autonomously adjusts its own output clock signal phase based on control information received from the multilevel receiver. Instead of requiring an external complex phase adjustment device, the system enables the clock generator to self-correct its phase timing, simplifying the overall device architecture while maintaining high restoration accuracy.
2Productivity
If multilevel signals are transmitted to improve data transfer rate, then transmission speed increases, but the probability of invalid signal generation increases
Solution Approach 1:
The multilevel receiver continuously monitors restored signals and generates control information indicating the presence of invalid signals. This feedback is sent to the clock generator, which adjusts the clock phase to minimize invalid signal generation. This dynamic feedback control enables the system to maintain high data transfer rates while automatically correcting phase errors that cause signal invalidity.
Solution Approach 2:
The patent dynamically changes the phase parameter of the clock signal based on the detected signal quality. By adjusting the phase timing parameter in response to invalid signal detection, the system optimizes the sampling points for multilevel signal restoration, thereby reducing the probability of invalid signal generation while maintaining high transmission speed.
3Measurement precision
If the clock signal phase is adjusted manually or with complex circuits, then signal restoration accuracy improves, but power consumption increases
Solution Approach 1:
The clock generator performs automatic self-adjustment of its clock signal phase based on simple control information from the receiver. This self-service mechanism eliminates the need for power-hungry external phase adjustment circuits or complex control logic, achieving accurate signal restoration with minimal additional power consumption.
Solution Approach 2:
The system uses a lightweight feedback mechanism where the receiver sends minimal control information about restoration accuracy to the clock generator. This simple feedback loop enables continuous optimization of signal restoration accuracy without requiring complex control circuits that would consume excessive power.
Data Source
AI summary
A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.