Semiconductor Interconnect Layout With Multi-Metal Vias and Power Lines
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved methods for fabricating devices with superior performance.
Innovation Solution
A semiconductor device design featuring distinct metallic materials for power lines, lower lines, and vias, with varying widths and tapered shapes to enhance electrical conductivity and reduce resistivity, combined with a gate dielectric layer using high-k dielectric materials and ferroelectric/paraelectric layers for improved capacitance control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent applies local quality by using different metallic materials for different interconnect levels (first interlayer dielectric layer uses first metallic material, second interlayer dielectric layer uses second metallic material) and varying line widths at different locations (wider power lines for current carrying, narrower signal lines for routing). This localized optimization maintains signal integrity and reduces resistance even as overall device dimensions are scaled down.
Solution Approach 2:
The patent employs composite materials by combining multiple metallic materials in the interconnect structure. The first metallic material and second metallic material are used in different interlayer dielectric layers, creating a composite interconnect system that leverages the advantageous properties of each material to maintain electrical performance despite device scaling.
2Reliability
If line width is increased to reduce resistance, then conductivity improves, but area occupied increases
Solution Approach 1:
The patent implements local quality by assigning different width characteristics to different interconnect elements. Power lines are designed with greater width to minimize resistance for high-current paths, while other interconnect lines maintain narrower widths for routing efficiency. This selective width optimization ensures adequate conductivity without unnecessarily increasing overall interconnect area.
Solution Approach 2:
The patent applies asymmetry by creating non-uniform line width distribution across the interconnect structure. The first power line has a first width while the first lower line has a second width, with the first width being greater than the second width. This asymmetric design optimizes current distribution and reduces resistance in critical paths without uniformly increasing area.
3Reliability
If different metallic materials are used for vias and lines, then electrical characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the interconnect structure into distinct segments filled with different metallic materials. The first interlayer dielectric layer contains first metallic material in its vias and lines, while the second interlayer dielectric layer contains second metallic material. This segmented approach allows independent optimization of each layer's electrical properties while managing manufacturing complexity through systematic material assignment.
Data Source
AI summary
Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.