Semiconductor Multiplexer Swing Conversion for Stable Duty Cycle

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Solution Overview

Problem

Conventional semiconductor multiplexers designed with a differential scheme for serializing input/output signals in the CML region require separate signal transmission lines and circuits, leading to increased size and production costs, and face challenges in maintaining a stable duty cycle ratio due to noise and phase distortion when using a single-ended scheme.

Innovation Solution

A semiconductor device employing a single-ended scheme with synchronization blocks and swing region converting blocks to synchronize and serialize input signals in the CMOS region, then convert them to the CML region for serialization, and back to CMOS for output, while using a specific mode entry control signal to manage power consumption and prevent distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a differential scheme is used for serializing input/output signals in the CML region, then signal transmission stability is improved, but device size and production costs increase due to separate signal transmission lines and circuits

Engineering Contradiction:
Improvesignal transmission stabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent introduces a swing region converting block as an intermediary component that converts CML region signals to CMOS region signals for transmission through the multiplexer, and then converts them back to CML region at the output. This mediator approach allows the use of single-ended CMOS transmission lines instead of differential CML lines, reducing device size while maintaining signal stability through the conversion process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If a single-ended scheme is used for serializing input/output signals, then device size and production costs are reduced, but duty cycle ratio stability deteriorates due to noise and phase distortion

Engineering Contradiction:
Improvedevice sizeVSAvoidduty cycle ratio stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the operating region parameter of the signals by converting from CML region to CMOS region for multiplexer transmission, and then converting back to CML region. This parameter change allows the system to operate in a region (CMOS) that is more tolerant to noise and phase distortion, thereby maintaining duty cycle ratio stability while using a compact single-ended scheme.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The swing region converting blocks act as intermediaries that protect the signal integrity by isolating the single-ended multiplexer from direct CML signals. The first converting block transforms CML signals to CMOS region before multiplication, and the second converting block restores them to CML region after multiplication, preventing noise and phase distortion from affecting the duty cycle ratio.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multi-phase clock signals are used to control the multiplexer operation, then signal serialization is achieved, but duty cycle ratio distortion occurs due to process, voltage, and temperature variations

Engineering Contradiction:
Improvesignal serialization capabilityVSAvoidduty cycle ratio consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the signal region parameter from CML to CMOS for the multiplexer operation phase. The CMOS region operation is less sensitive to PVT variations compared to CML region, allowing the multi-phase clock signals to control the multiplexer effectively while maintaining consistent duty cycle ratio despite process, voltage, and temperature changes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7830282B2Semiconductor device
Publication Date: 2010.11.09 SK HYNIX INC
  • US7830282B2 patent drawing
  • US7830282B2 patent drawing
  • US7830282B2 patent drawing

AI summary

A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region.