Semiconductor Device N++-Type Layer Current Concentration
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Solution Overview
Problem
In power converters, parallel-connected IGBT elements experience current concentration due to varying on-voltages, leading to potential breakdown, especially when on-voltage has a negative temperature coefficient, and reducing P-type collector layer impurity concentration to mitigate this results in lower interruptable current values during short circuits.
Innovation Solution
A semiconductor device structure with an N++-type layer having higher impurity concentration than the N-type buffer layer and equal to or higher than the P-type collector layer, reducing hole injection and stabilizing on-voltage, is implemented to minimize current concentration and prevent breakdown in parallel connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If on voltage has negative temperature coefficient to improve conductivity, then power losses are reduced, but current concentration occurs when temperatures vary in parallel connections
Solution Approach 1:
The patent changes the temperature coefficient parameter by controlling the impurity concentration distribution, specifically creating an N++-type layer with 1×10^19 to 1×10^20 atoms/cm³ and P-type collector layer with 1×10^16 to 1×10^18 atoms/cm³. This parameter configuration shifts the on voltage temperature coefficient from negative to positive, ensuring that as temperature increases, on voltage increases, which prevents current concentration in parallel connections while maintaining acceptable power loss characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced hole injection and stabilized on-voltage prevent current concentration-induced breakdowns and maintain interruptable current values, even under temperature variations, while ensuring the semiconductor device's reliability and stability in parallel connections.
Implementation Method 1
the amount of holes to be injected from a lower surface side of the semiconductor device is reduced
Data Source
AI summary
A semiconductor device includes, on an upper surface side of an N−-type drift layer, a P-type well layer, an N-type emitter layer, a gate insulation film, and a gate electrode, and includes, on a lower surface side of the N−-type drift layer, an N-type buffer layer, a P-type collector layer, and an N++-type layer. The N++-type layer is partially formed in the N-type buffer layer. The N++-type layer has impurity concentration being higher than impurity concentration of the N-type buffer layer and being equal to or higher than impurity concentration of the P-type collector layer.