Semiconductor Nanosheet Separation Walls for Lower Parasitic Capacitance
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Solution Overview
Problem
The demand for high integration of semiconductor devices leads to a short channel effect in transistors, reducing the reliability of integrated circuit devices, which existing multi-gate structures like nanosheet-type transistors have not adequately addressed.
Innovation Solution
A semiconductor device design featuring a fin-type active area with nanosheet stacks separated by a nanosheet separation wall and gate lines, including a gate separation spacer to isolate nanosheet stacks, and a gate cut structure to enhance separation, improving operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet stacks are arranged closely for high integration, then device density increases, but parasitic capacitance increases and reliability decreases
Solution Approach 1:
The patent divides the continuous nanosheet structure into separate stacks using nanosheet separation walls. These walls physically segment the nanosheets, reducing capacitive coupling between adjacent stacks while maintaining high integration density through optimized spacing and arrangement of the separated stacks.
Solution Approach 2:
The nanosheet separation walls act as intermediary structures between adjacent nanosheet stacks. These walls provide electrical isolation and reduce parasitic capacitance by serving as dielectric barriers, thereby improving transistor reliability without compromising the overall device density.
2Ease of manufacture
If gate lines extend continuously over nanosheet stacks, then manufacturing is simplified, but parasitic capacitance between adjacent gates increases
Solution Approach 1:
The continuous gate line is segmented into separate gate electrodes by gate cut structures. These cuts divide the gate line into discrete sections that align with individual nanosheet stacks, reducing parasitic capacitance between adjacent gates while maintaining manufacturing feasibility through standard photolithography patterning processes.
Solution Approach 2:
The gate cut structures introduce a dimensional change by creating discontinuities in the gate line at specific locations. This dimensional modification (from continuous to discontinuous) reduces capacitive coupling in the horizontal direction while the gate electrodes still provide vertical control over the nanosheet channels.
Data Source
AI summary
A semiconductor device includes a substrate including a fin-type active area and a device separation layer configured to cover both sidewalls of the fin-type active area, a pair of nanosheet stacks each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack, an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack, a nanosheet separation wall arranged between each of the pair of nanosheet stacks and extending in a first horizontal direction, and a pair of gate lines extending on the pair of nanosheet stacks in a second horizontal direction, wherein the nanosheet separation wall separates respective lower nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction.