Semiconductor Nanowire Fabrication via Selective Etching
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Solution Overview
Problem
Current methods for fabricating semiconductor devices face challenges in effectively forming and scaling multigate transistors, particularly in suppressing short channel effects and enhancing current control without increasing gate length, while maintaining device density.
Innovation Solution
A method involving the formation of a stacked structure with alternately stacked sacrificial and semiconductor layers, followed by the creation of dummy gate structures and spacer films with different materials to form recesses and control the etching process, allowing for the precise formation of nanowires and spacers that enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate length is increased to suppress short channel effects, then current control capability is improved, but device density is reduced
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional multigate structures (FinFET, nanowire, cage-like gates) that wrap around the channel in multiple directions. This dimensional change provides superior electrostatic control and short channel effect suppression without requiring increased gate length, thereby maintaining high device density while improving current control capability.
Solution Approach 2:
The patent employs composite material structures including stacked semiconductor layers with different materials (e.g., Si/SiGe), combined gate materials (TiN, TaN, W), and multi-layer spacer films with different etch selectivities. These composite structures enable precise control of electrical properties and facilitate complex fabrication processes while maintaining device performance and density.
2Productivity
If multigate transistor structures are formed to increase device density, then scaling is improved, but fabrication complexity increases
Solution Approach 1:
The patent divides the fabrication process into multiple discrete stages: forming stacked sacrificial and semiconductor layers, creating dummy gate structures, performing selective etching to form recesses, depositing multiple spacer films with different materials, and selective removal of spacer portions. Each stage builds upon the previous one, systematically constructing the complex multigate structure while maintaining process control and repeatability.
Solution Approach 2:
The patent introduces dummy gate structures and sacrificial layers as intermediary elements that facilitate the formation of complex multigate structures. These intermediaries are temporarily formed to enable precise patterning and spacer deposition, then selectively removed to reveal the final gate structures. This approach simplifies the overall fabrication by breaking down complex steps into manageable intermediate stages.
3Manufacturing precision
If spacer films with different materials are used to form precise structures, then manufacturing precision is improved, but process steps increase
Solution Approach 1:
The patent applies different material properties to different regions and stages of the fabrication process. Multiple spacer films with distinct etch selectivities are deposited sequentially, with each material chosen for its specific role in subsequent selective removal steps. This local differentiation of material properties enables precise control over which structures remain and which are removed, achieving high manufacturing precision through targeted material selection.
Solution Approach 2:
The patent utilizes changes in material parameters, particularly etch selectivity, to control the fabrication process. By selecting materials with vastly different etch rates to specific chemicals, the process enables selective removal of sacrificial layers, dummy gates, and spacer portions while preserving other structures. This parameter-based control allows precise structure formation without requiring additional complex patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved scaling and current control in semiconductor devices by effectively suppressing short channel effects and maintaining device density, leading to enhanced transistor performance and reliability.
Implementation Method 1
forming a recess by etching the stacked structure using the dummy gate structure as a mask
Implementation Method 2
conformally forming a first spacer film on the sacrificial layer and the semiconductor layer of the first exposed region
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.