Semiconductor Device With Narrowed Lower Contact Width
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing density and controlling current without increasing gate length, while also suppressing short channel effects, which affect the electric potential of the channel region.
Innovation Solution
The semiconductor device design includes multiple active regions with specific gate structures and contacts, where the width of the lower contact on the active regions is narrower than on the element isolation regions, and the upper contact width is narrower than the lower contact width, ensuring reliable contact and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is increased to enhance current control capability, then current control capability is improved, but device density is reduced
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional multigate control by forming gates on multiple surfaces of the semiconductor body (front surface, side surfaces, and rear surface). This dimensional change enables enhanced current control through increased gate surface area without increasing gate length, thereby improving current control capability while maintaining high device density.
Solution Approach 2:
The patent implements nested gate structures where inner gates are positioned within outer gates, creating a concentric multigate configuration. This nesting arrangement maximizes the gate surface area that can control the channel from multiple directions, enhancing current control capability without increasing the overall device footprint, thus maintaining high device density.
2Reliability
If the gate length is increased to suppress short channel effects, then short channel effects are suppressed, but device density is reduced
Solution Approach 1:
The patent employs three-dimensional multigate structures that control the channel from front, side, and rear surfaces simultaneously. This multi-directional control effectively suppresses short channel effects by reducing the electric field influence from drain to source, achieving excellent SCE suppression without increasing gate length, thereby maintaining high device density.
Solution Approach 2:
The patent utilizes composite semiconductor structures including semiconductor bodies with specific crystal orientations (e.g., <110> or <100>) and engineered doping profiles combined with multigate configurations. This composite approach enhances short channel effect suppression through material property optimization while maintaining compact device dimensions for high density.
Data Source
AI summary
A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.