Semiconductor Structure NBTI Reduction via Fluorine Diffusion
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Solution Overview
Problem
Semiconductor devices face reliability issues due to negative bias temperature instability (NBTI) in metal-oxide semiconductor field-effect transistors (MOSFETs), particularly with the use of high-k gate dielectrics, which can lead to performance degradation over time, especially in sub-micron regimes.
Innovation Solution
A method involving the diffusion of fluorine atoms into the semiconductor structure through an anneal in a fluorine-containing gas, followed by a high temperature anneal in a reducing environment, to improve NBTI by incorporating fluorine and hydrogen/deuterium atoms into the interfacial layer, thereby reducing instability in MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate dielectric materials are used to improve gate current density and electrical performance in sub-micron devices, then electrical performance is improved, but negative bias temperature instability (NBTI) occurs leading to threshold voltage drift and performance degradation over time
Solution Approach 1:
A passivation layer comprising silicon nitride and silicon oxynitride is introduced as an intermediary between the high-k gate dielectric and the channel. This passivation layer acts as a mediator that prevents harmful interactions while maintaining the electrical benefits of high-k materials, specifically reducing NBTI effects by stabilizing the interface
Solution Approach 2:
The gate stack employs composite materials including high-k dielectric (such as hafnium oxide), silicon nitride, and silicon oxynitride in a layered structure. This composite approach combines the high gate current density capability of high-k materials with the stability and NBTI reduction properties of nitride-based layers
2Productivity
If gate dielectric thickness is reduced to enable further device scaling, then device density is improved, but time-related voltage breakdowns and hot carrier effects occur adversely affecting transistor stability
Solution Approach 1:
The gate dielectric structure uses a composite of high-k material and nitride-based passivation layers, enabling thinner effective oxide thickness for higher device density while the nitride layer provides robustness against voltage breakdown and hot carrier effects
Solution Approach 2:
The silicon nitride and silicon oxynitride passivation layer is deposited beforehand to cushion and protect the thin gate dielectric interface from harmful effects before the device operates, preventing time-related voltage breakdowns and hot carrier induced degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces NBTI by enhancing the stability of semiconductor devices, improving the electrical performance and reliability of MOSFETs by driving fluorine and reducing gas atoms into the interfacial layers, which helps in mitigating the performance degradation associated with high-k gate dielectrics.
Implementation Method 1
diffusing fluorine atoms into a semiconductor structure by an anneal in a fluorine containing gas
Implementation Method 2
performing an anneal in a reducing environment followed by a high temperature anneal
Data Source
AI summary
An approach to forming a semiconductor structure with improved negative bias temperature instability includes diffusing fluorine atoms into a semiconductor structure by an anneal in a fluorine containing gas. The approach includes removing a pFET work function metal layer from an area above an nFET wherein the area above the nFET includes at least the area over the nFET. Additionally, the approach includes depositing a layer of nFET work function metal on a remaining portion of the pFET work function metal and depositing a gate metal over the nFET work function metal layer. Furthermore, the method includes performing an anneal in a reducing environment followed by a high temperature anneal.