Semiconductor Patterning via Negative Spacer Process
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce the manufacturing cost by minimizing the number of mask processes required for forming fine patterns, as existing methods like Double Patterning Technology (DPT) and Spacer Patterning Technology (SPT) face limitations in reducing costs and misalignment issues.
Innovation Solution
A method involving a negative spacer patterning process that forms sacrificial film patterns and pad patterns with a critical dimension ratio of 1:3, followed by forming spacers and a gap-fill layer, allowing for the reduction of mask processes to two, thereby reducing manufacturing costs by eliminating unnecessary steps and misalignment problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Double Patterning Technology (DPT) is used to form fine patterns, then the critical dimension can be reduced to half, but the number of mask processes increases to four, thereby increasing manufacturing cost and complexity
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into two distinct stages: first forming sacrificial film patterns with a 1:3 line-space ratio, then forming spacers on these patterns to create the final fine patterns. This segmentation allows achieving half critical dimension through a simplified two-mask process rather than the conventional four-mask DPT process.
Solution Approach 2:
The patent uses spacers as an intermediary element between the sacrificial film patterns and the final target pattern. The spacers are formed on the sacrificial films and serve as the actual patterning mask for the subsequent etching process, eliminating the need for additional photoresist coating and exposure steps required in conventional DPT.
2Manufacturing precision
If conventional lithography process is used with short wavelength light source, then the resolution can be improved, but the process constant reaches physical limit making it difficult to form patterns at critical dimension equal to wavelength or less
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation. By utilizing the vertical dimension to form spacers on sacrificial film patterns, the process achieves sub-wavelength resolution without being constrained by the optical diffraction limit of conventional lithography. The spacer width is determined by deposition thickness rather than optical exposure parameters.
3Device complexity
If Spacer Patterning Technology (SPT) is used to reduce mask processes to two, then manufacturing cost is reduced, but misalignment issues and process complexity remain
Solution Approach 1:
The patent performs preliminary action by first forming sacrificial film patterns with optimized 1:3 line-space ratios, then forming spacers on these pre-formed structures. This preliminary sacrificial film formation establishes a stable foundation that ensures proper spacer placement and width, thereby preventing misalignment issues in the subsequent patterning steps.
Solution Approach 2:
The patent changes the critical parameter from photoresist pattern dimensions (constrained by optical resolution) to spacer thickness (controlled by deposition processes). This parameter change from lateral to vertical dimension control enables better precision and reduces misalignment, as spacer thickness can be controlled with atomic-layer precision through ALD or CVD processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the manufacturing cost of semiconductor devices by completing patterning through only two mask processes, enhancing efficiency and minimizing misalignment, while achieving a ½ critical dimension for sacrificial film patterns.
Implementation Method 1
coating a photoresist over a substrate, performing an exposure process on the photoresist using an exposure mask having the fine patterns defined therein using a light source having a wavelength such as 365 nm, 248 nm, 193 nm, and 153 nm
Data Source
AI summary
A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region.