Semiconductor IC Noise Tolerance Evaluation via Pseudo-Random Pattern
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Solution Overview
Problem
Existing semiconductor integrated circuit devices lack effective methods for evaluating noise tolerance, which is crucial for ensuring reliable operation under noisy conditions.
Innovation Solution
The evaluation system incorporates a pseudo-random pattern generator and an expected value generator synchronized by a clock signal, with a detector to identify malfunctions due to noise by comparing outputs, allowing for real-time assessment of noise tolerance through external terminals and various disturbance applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pseudo-random pattern generator is added to the semiconductor integrated circuit device, then noise tolerance evaluation capability is improved, but device complexity increases
Solution Approach 1:
The pseudo-random pattern generator is designed to serve multiple functions: it generates test patterns for noise tolerance evaluation, provides clock signals for synchronization, and outputs evaluation results through external terminals. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while improving noise tolerance evaluation capability.
Solution Approach 2:
The semiconductor integrated circuit device performs self-evaluation of noise tolerance by incorporating the pseudo-random pattern generator internally. The device generates its own test patterns and evaluates its own noise resistance without requiring external testing equipment, thereby improving evaluation capability while avoiding the complexity of external testing systems.
2Reliability
If flip-flops are dispersed and additional components like composite cells and antenna diodes are added, then noise resistance is improved, but device complexity increases
Solution Approach 1:
The device disperses flip-flops across different locations within the semiconductor integrated circuit rather than concentrating them in one area. This segmentation reduces the impact of localized noise events on multiple flip-flops simultaneously, improving noise resistance. The dispersed arrangement also allows for better spatial distribution of additional protective components.
Solution Approach 2:
Antenna diodes and composite cells are added at specific locations where noise susceptibility is highest, rather than uniformly across the entire device. This localized approach provides targeted noise protection where most needed, improving overall noise resistance while minimizing the total number of additional components required.
Data Source
AI summary
Provided is a semiconductor integrated circuit device including a pseudo-random pattern generator configured to output a pseudo-random pattern, a terminal for externally outputting an output of the pseudo-random pattern generator or an evaluation result of noise tolerance evaluated on the basis of the pseudo-random pattern.