Semiconductor Device Non-Implant Doping for Large Display Panels
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Solution Overview
Problem
Conventional low-temperature polycrystalline silicon (LTPS) thin film transistor devices face issues with poor uniformity and damage to semiconductor layers during the formation of N-type and P-type doped layers, leading to deteriorated device characteristics and high fabrication costs due to the use of ion implant processes.
Innovation Solution
A semiconductor device and method that uses a non-implant process to form doped layers, employing a first dielectric layer to protect the semiconductor layer in one region and an etching stop layer in another, allowing for the formation of both N-type and P-type doped layers without damaging the polycrystalline silicon layer, and integrating an annealing process to reduce resistance, thus improving electrical performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implant process is used to form doped layers, then contact resistance is reduced, but device complexity and fabrication cost increase
Solution Approach 1:
The patent replaces the ion implantation process (mechanical/physical system) with a chemical vapor deposition process using silane gas and phosphine gas. This substitution eliminates the need for complex ion implantation equipment while achieving the same doping effect, thereby reducing device complexity and fabrication cost while maintaining low contact resistance.
2Adaptability or versatility
If both N type and P type doped layers are formed using conventional process, then device functionality is achieved, but semiconductor layer is damaged multiple times
Solution Approach 1:
The patent performs preliminary patterning of the semiconductor layer into separate N-type and P-type regions before forming the doped layers. This preliminary action eliminates the need for subsequent etching processes that would damage the semiconductor layer, as the regions are already defined and isolated. The first doped layer is then formed in the N-type region, followed by the second doped layer in the P-type region, without requiring additional etching steps that would compromise layer integrity.
3Reliability
If conventional LTPS process is used for large-size display panel fabrication, then electrical mobility is improved, but uniformity deteriorates
Solution Approach 1:
The patent employs laser annealing with specific parameters (wavelength, power, scanning speed) to treat the semiconductor layer after deposition. This parameter optimization enables crystallization and doping simultaneously, achieving high electrical mobility while maintaining uniformity across large-area substrates. The controlled laser parameters ensure consistent treatment across the entire display panel surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces the risk of semiconductor layer damage, enhances electrical performance, and lowers fabrication costs by eliminating the need for extra processes, making it suitable for large-size display panel fabrication.
Implementation Method 1
integrating an annealing process to reduce resistance
Data Source
AI summary
A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.