Semiconductor Device Non-Volatile Memory High Speed Read
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Solution Overview
Problem
Conventional semiconductor devices for embedded flash memory struggle with slow read operations, which hinders the efficiency of data retrieval and increases power consumption.
Innovation Solution
The semiconductor device incorporates a bit line selection circuit with parallel sub-select transistors and a sense amplifier with an active load, including a PMOS or NMOS diode, to rapidly transfer read current and compare it with a reference current, enabling faster data reading by maintaining a constant bit line voltage and reducing input voltage for high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional read operation is used, then device complexity is reduced, but read operation speed is slow
Solution Approach 1:
The bit line selection circuit is segmented into multiple sub-select transistors (first sub-select transistor, second sub-select transistor, third sub-select transistor, fourth sub-select transistor) that can be independently controlled. Each transistor is associated with a separate gate control signal, allowing parallel operation and faster bit line selection, thereby increasing read operation speed without excessive complexity increase
Solution Approach 2:
The bit line selection circuit dynamically switches between different transistor configurations based on operation mode. During read operations, the circuit activates specific sub-select transistors to create optimal current paths, enabling fast and variable-speed read operations adapted to different performance requirements
2Speed
If read current transfer is accelerated, then read operation speed is improved, but power consumption increases
Solution Approach 1:
The sense amplifier pre-charges the bit line voltage before the actual read operation begins. This preliminary voltage establishment reduces the voltage drop during data reading, allowing faster current transfer while minimizing power consumption by avoiding excessive voltage stress during the read operation
Solution Approach 2:
The circuit dynamically adjusts bit line voltage levels and current transfer parameters based on the specific read operation requirements. By optimizing voltage and current parameters in real-time, the system achieves high-speed data reading while minimizing power consumption through efficient parameter management
3Speed
If bit line voltage is maintained constant, then read operation speed is improved, but device complexity increases
Solution Approach 1:
The sense amplifier incorporates feedback mechanisms that continuously monitor bit line voltage and current conditions. This feedback enables automatic voltage maintenance and compensation, ensuring constant voltage during read operations while keeping the control logic manageable through intelligent regulation rather than complex rigid control circuits
Data Source
AI summary
A semiconductor device includes a memory cell array including a plurality of memory cells, a bit line selection circuit, including a first main select transistor, and a plurality of first sub-select transistors connected in parallel with each other, and the plurality of first sub-select transistors configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell, and output an output signal based on an input voltage, the sense amplifier including an active load, connected to the first main select transistor, comprising a PMOS diode or a NMOS diode configured to lower the input voltage at a sense node.