Semiconductor Device N-Well P-Well Decoupling Capacitor
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing power supply noise at high frequencies due to parasitic resistance in decoupling capacitors, which limits their frequency applicability and increases mounting area, reducing integration density.
Innovation Solution
A semiconductor device configuration with buried P wells and alternately arranged N wells, where the width of the N well contact region with the buried P well is limited to 2 μm or less, allowing for reduced resistance and the formation of a decoupling capacitor applicable to high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoupling capacitor with sufficient capacitance (several ten nano-farads) is arranged to suppress power supply voltage fluctuation, then power supply noise is reduced and circuit operation is stabilized, but mounting area increases and degree of integration reduces
Solution Approach 1:
The invention merges the decoupling capacitor function with the existing well structures (N-well and P-well) that are already present in the semiconductor device. By utilizing the contact surface between the N-well and P-well, along with the substrate, the capacitor is formed within the existing device structure rather than as a separate component, thereby eliminating the need for additional mounting area while maintaining the power supply noise suppression function
Solution Approach 2:
The well structures (N-well and P-well) serve dual purposes: they function as active device regions for circuit operation and simultaneously serve as the capacitor electrodes for power supply noise suppression. This multi-functionality allows the same structural elements to fulfill both computational and decoupling roles, resolving the contradiction between reliability and mounting area
2Quantity of substance
If the N well width is increased to provide sufficient capacitance, then capacitor capacity increases, but parasitic resistance increases and frequency characteristics deteriorate
Solution Approach 1:
The invention applies different conductivity types to different regions (N-well and P-well alternating arrangement) to create localized capacitive effects. By configuring the N-well and P-well with alternating polarity and appropriate dimensions, sufficient capacitance is achieved through the combined effect of multiple localized capacitor components formed at each N-well/P-well interface, rather than relying on a single large-width well
Solution Approach 2:
The decoupling capacitor is segmented into multiple smaller capacitor components formed at each contact surface between alternating N-wells and P-wells. This segmentation allows the total capacitance to be distributed across multiple interfaces, each with small dimensions that minimize parasitic resistance, thereby maintaining high-frequency characteristics while achieving the required total capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic resistance, enabling decoupling capacitors to function effectively at high frequencies, thus preventing erroneous operations and maintaining high integration density.
Implementation Method 1
a capacitor between the power supply voltage Vcc and the ground voltage Vss is formed on the contact surface between the N well and P well
Implementation Method 2
a pn junction is formed between the substrate and an inverse-conductivity-type epitaxial layer formed thereon to form a capacitor
Data Source
AI summary
A width of a region where each of the N wells is in contact with the buried P well is not more than 2 μm. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.