Semiconductor N-well Spacing via Segmented P-wells
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Solution Overview
Problem
In miniaturized semiconductor devices, the interval between N-wells is difficult to shorten due to punch-through issues and insufficient breakdown voltage, especially when high voltages are applied, as conventional structures with offset regions and epitaxial layers limit the reduction of N-well spacing and increase the risk of deep implantation-induced defects.
Innovation Solution
A semiconductor device structure with multiple conductivity type wells, including a P-type semiconductor substrate with N-wells, a P-well, and additional P-wells with specific impurity concentration peaks, allowing for ion implantation to enhance breakdown voltage and reduce well spacing, while minimizing adverse effects on resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interval between N-wells is shortened to miniaturize the semiconductor device, then the device size is reduced, but punch-through occurs between N-wells and breakdown voltage is insufficient
Solution Approach 1:
The patent divides the P-type substrate into multiple P-well regions with different impurity concentrations. Specifically, it creates a first P-well region with higher impurity concentration and a second P-well region with lower impurity concentration, forming a segmented structure that prevents punch-through while maintaining compact dimensions. This segmentation allows each region to serve a specific function in voltage blocking and charge management.
Solution Approach 2:
The patent applies local quality by creating P-well regions with spatially varying impurity concentrations. The first P-well region has a higher impurity concentration near the N-wells to provide strong electric field shielding, while the second P-well region has a lower impurity concentration deeper in the substrate to maintain overall electrical properties. This local variation in impurity concentration optimizes breakdown voltage at each location.
2Reliability
If offset regions and P-type epitaxial layers are used to prevent punch-through, then breakdown voltage is improved, but the interval between N-wells cannot be reduced
Solution Approach 1:
The patent changes the impurity concentration parameter of the P-well regions to achieve both punch-through prevention and reduced N-well spacing. By adjusting the impurity concentration in the first and second P-well regions, the patent optimizes the electric field distribution to maintain high breakdown voltage while allowing closer N-well placement, eliminating the need for large offset regions.
3Reliability
If N+ diffusion layers are formed on N-wells for contact connection, then electrical connection is improved, but channeling occurs and deeply-implanted N-wells are formed causing additional punch-through
Solution Approach 1:
The patent applies preliminary anti-action by forming the first and second P-well regions with specific impurity concentrations before the N+ diffusion process. These pre-formed P-well regions create an electric field configuration that counteracts the channeling effect during subsequent N+ ion implantation, preventing deeply-implanted N-wells from forming and causing additional punch-through while maintaining good electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively improves the separation breakdown voltage between N-wells, enabling a shorter interval and maintaining voltage integrity even under high voltage conditions, with minimal adverse effects on well resistance and junction capacitance.
Implementation Method 1
implanting ions into the entire surface of a first conductivity type semiconductor substrate to form a first conductivity type fourth well; and implanting ions into the entire surface of the semiconductor substrate to form a first conductivity type third well
Data Source
AI summary
To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate 1, second conductivity type first wells 2 and 3 disposed on a surface layer of the semiconductor substrate 1 with a predetermined interval between them, a first conductivity type second well 4 disposed between the first wells 2 and 3 on the surface layer of the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third well 5 at least disposed below the second well 4 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4, and a first conductivity type fourth well 11 at least disposed below the third well 5 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4.