Semiconductor Device With Offset Gate Electrode
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high on-state current and low off-state current while maintaining a high degree of integration and durability, particularly in transistors used in display and integrated circuits, due to issues with parasitic capacitance and leakage current.
Innovation Solution
The semiconductor device design incorporates a specific structure with overlapping and non-overlapping conductor regions, a semiconductor with varying electron affinity layers, and insulators with different relative permittivities to optimize electrical characteristics, including a fringe electric field-induced carrier contribution for enhanced on-state current and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased in a semiconductor device, then the device complexity and functionality are improved, but parasitic capacitance formed by overlap between wirings, electrodes, and the like increases and has a non-negligible effect
Solution Approach 1:
The patent extracts the harmful overlapping region between the gate electrode and source/drain electrodes by introducing an offset region. The gate electrode is positioned to overlap only with the channel-forming region of the semiconductor, deliberately excluding overlap with the source and drain electrodes. This separation removes the parasitic capacitance source while preserving the essential gate-channel control function.
Solution Approach 2:
The patent segments the electrode regions into distinct functional zones: a gate electrode region overlapping with the channel, and separate source/drain electrode regions with offset from the gate. This segmentation allows independent optimization of each region's function, enabling the gate to control the channel while minimizing unwanted capacitive coupling with the source and drain.
2Productivity
If transistors are decreased in size to be integrated in an integrated circuit, then the device complexity and integration are improved, but leakage current in off state increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar transistor structure to a three-dimensional structure where the gate electrode wraps around or overlaps with the side surfaces of the semiconductor channel. This vertical/dimensional extension of gate control provides better electrostatic control over the channel, suppressing leakage current while allowing horizontal miniaturization for higher integration density.
3Object-generated harmful factors
If a transistor structure with offset region is used to reduce parasitic capacitance, then the harmful parasitic capacitance is reduced, but the on-state current may be limited due to reduced overlap between gate and channel
Solution Approach 1:
The patent compensates for the horizontal offset between gate and source/drain electrodes by extending gate control into the vertical dimension. The gate electrode is designed to overlap with the side surfaces of the semiconductor channel, creating a three-dimensional control region. This vertical extension maintains strong electrostatic control for high on-state current while preserving the horizontal offset that reduces parasitic capacitance.
Solution Approach 2:
The patent creates a nested structure where the gate electrode wraps around or envelops portions of the semiconductor channel from multiple directions. This nested configuration provides comprehensive gate control over the channel region, ensuring sufficient overlap for high on-state current while maintaining the offset geometry that minimizes parasitic capacitance with source and drain electrodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a high on-state current and low off-state current, enabling highly integrated and durable semiconductor devices with improved electrical performance.
Implementation Method 1
a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator
Implementation Method 2
the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween
Implementation Method 3
a fringe electric field-induced carrier contribution for enhanced on-state current and reduced parasitic capacitance
Implementation Method 4
a semiconductor device including a semiconductor, an insulator, a first conductor, and a second conductor
Data Source
AI summary
A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.