Semiconductor Fabrication Using Offset Spacers for Source/Drain Regions
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Solution Overview
Problem
The manufacturing costs of semiconductor devices are increased due to the need to fabricate semiconductor elements separately in cell and peripheral circuit regions, which have different structures, sizes, and distances, requiring additional processing steps and potentially increasing complexity.
Innovation Solution
A method involving the formation of gate structures, offset spacers, and multi-layered spacers to facilitate ion implantation for source/drain region formation without additional photomasks, allowing for simultaneous processing of both regions with precise control over spacer thickness and etch selectivity to minimize short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication processes are used for cell region and peripheral circuit region, then each region can be optimized for its specific structure and size requirements, but manufacturing costs increase and process complexity increases
Solution Approach 1:
The patent applies local quality by forming different types of spacers (first spacer in cell region, second spacer in peripheral circuit region) with different materials and thicknesses in different regions of the semiconductor device. This allows each region to have optimized local characteristics - the first spacer prevents short channel effects in the cell region while the second spacer provides appropriate spacing in the peripheral circuit region, thereby achieving region-specific optimization without requiring completely separate fabrication processes
Solution Approach 2:
The patent segments the fabrication process into distinct stages: forming the first spacer only in the cell region, then forming the second spacer only in the peripheral circuit region. This segmentation allows each region to receive targeted processing appropriate to its specific requirements while still using a unified overall fabrication approach, reducing both cost and complexity compared to fully separate processes
2Manufacturing precision
If separate fabrication processes are used for cell region and peripheral circuit region, then each region can be optimized for its specific structure and size requirements, but manufacturing costs increase
Solution Approach 1:
The patent merges the fabrication processes for the cell region and peripheral circuit region into a unified process flow. Both regions share common process steps including substrate preparation, gate formation, and spacer formation, while incorporating region-specific variations only where necessary. This merging reduces the total number of separate fabrication sequences needed, thereby lowering manufacturing costs while still achieving region-optimized structures
3Manufacturing precision
If additional photomasks are used for separate region processing, then precise control over different region structures can be achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs preliminary action by forming the first spacer in the cell region before forming the second spacer in the peripheral circuit region. This sequential approach allows each spacer to be formed with precise thickness control using standard deposition techniques without requiring additional photomask patterns. The preliminary formation of the first spacer establishes a foundation that guides subsequent processing, achieving precise control while minimizing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of semiconductor devices with reduced manufacturing costs and improved performance by allowing for the simultaneous formation of source/drain regions in both cell and peripheral circuit regions without additional photomasks, achieving excellent device performance and reducing short channel effects.
Implementation Method 1
performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantation mask
Implementation Method 2
etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material
Data Source
AI summary
A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.