Semiconductor Source/Drain Contact With Offset Via Landing
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Solution Overview
Problem
As integrated circuits shrink and become more densely packed, connecting source/drain contacts to interconnect levels becomes challenging due to increased density, leading to potential shorts and reduced design flexibility.
Innovation Solution
A method is developed to form source/drain contacts with horizontally offset via landing portions, allowing for reduced routing tracks and increased design flexibility, while maintaining electrical insulation and minimizing the risk of shorts by using a combination of deep and shallow contact openings and spacer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuits are miniaturized and densely packed, then device density and functionality are improved, but the risk of shorts between source/drain contacts and other conductive structures increases
Solution Approach 1:
The patent introduces a horizontal offset dimension for the via landing portion, moving it away from the vertical alignment above the semiconductor structure. This dimensional change allows the contact to be made at a position between adjacent semiconductor structures, reducing the risk of shorts while maintaining device density.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the source/drain contact and adjacent conductive structures. This intermediary layer provides electrical isolation, preventing shorts while allowing the contact to extend horizontally closer to other structures.
2Ease of manufacture
If via landing portions are vertically aligned above semiconductor structures, then manufacturing simplicity is maintained, but design flexibility for routing connections is reduced
Solution Approach 1:
The contact structure is segmented into two distinct portions: a vertically extending contact portion for electrical connection and a horizontally extending via landing portion for routing connection. This segmentation allows each portion to be optimized independently - the contact portion maintains vertical alignment for manufacturing simplicity while the via landing portion can be positioned horizontally for routing flexibility.
Solution Approach 2:
The via landing portion extends in the horizontal direction, adding a lateral dimension to the connection geometry. This allows routing tracks to be positioned at horizontal locations between semiconductor structures, providing design flexibility without compromising the vertical alignment simplicity of the contact portion.
3Length of stationary object
If horizontal routing tracks are positioned between semiconductor structures, then cell height is reduced, but the complexity of forming precise horizontal connections increases
Solution Approach 1:
The via landing portion is formed as part of the source/drain contact structure before the routing tracks are formed. This preliminary action establishes the horizontal connection point in advance, simplifying the subsequent routing formation process and reducing the complexity of forming precise horizontal connections.
Solution Approach 2:
The via landing portion acts as an intermediary structure that bridges the vertical contact and the horizontal routing track. It provides a predefined connection point that simplifies the routing formation process, reducing the complexity of forming precise horizontal connections between semiconductor structures.
Data Source
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AI summary
According to an aspect of the present inventive concept there is provided a semiconductor device comprising: a substrate; a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: - a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and - a via landing portion protruding horizontally from the vertically extending contact portion in a second horizontal direction towards the second semiconductor structure, to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure; and an interconnection level including a first vertical via abutting the via landing portion.