Semiconductor Device Offset Voltage Suppression via Signal Segmentation
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Solution Overview
Problem
Existing semiconductor devices used for grayscale voltage generation in display devices face challenges such as increased circuit area and reduced response speed due to the exponential increase in the number of switches with higher bit digital signals, and are prone to offset voltage issues that degrade display quality.
Innovation Solution
A semiconductor device with a novel structure incorporating a digital-to-analog converter circuit, differential amplifier circuits, a current-voltage converter circuit, and a switching circuit, which generates analog signals by separately processing upper and lower bit digital signals, reducing the number of resistors and parasitic capacitance, and mitigates offset voltage effects through switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits of digital signals is increased to achieve higher performance display, then the grayscale resolution is improved, but the circuit area increases exponentially due to the exponential increase in the number of switches
Solution Approach 1:
The patent divides the N-bit digital signal into upper (N-M)-bit and lower M-bit signals, processing them through separate pathways. The upper bits control a first differential amplifier circuit while the lower bits control a second differential amplifier circuit, allowing independent processing that reduces the exponential growth of switches required for high-resolution grayscale generation.
Solution Approach 2:
The patent transitions from a single-dimensional R-DAC approach to a two-dimensional architecture by introducing both differential amplifier circuits operating in parallel with different bit assignments. This dimensional expansion allows high grayscale resolution to be achieved without proportionally increasing the number of switches in a single chain.
2Measurement precision
If the number of switches is increased to support higher bit digital signals, then the grayscale resolution is improved, but the response speed decreases due to increased parasitic capacitance
Solution Approach 1:
By segmenting the digital signal processing into two separate differential amplifier circuits handling different bit ranges, the patent reduces the number of switches in each individual circuit path. This segmentation directly reduces the total parasitic capacitance at the output portion, thereby improving response speed while maintaining high grayscale resolution through the combined output of both circuits.
Solution Approach 2:
The patent processes only the necessary portion of digital signals through each differential amplifier circuit - the upper bits through the first circuit and the lower bits through the second circuit. This partial processing approach avoids the excessive number of switches that would be required if all N bits were processed through a single R-DAC chain, thus reducing parasitic capacitance and improving response speed.
3Ease of manufacture
If a conventional D/A converter structure is used, then the circuit implementation is straightforward, but offset voltage of transistors degrades display quality
Solution Approach 1:
The patent incorporates feedback mechanisms within the differential amplifier circuits to compensate for transistor offset voltages. The differential architecture inherently provides feedback that balances the output, reducing the impact of offset voltages on the final analog signal and thereby maintaining high display quality without complicating the overall circuit implementation.
Solution Approach 2:
The differential amplifier circuits serve as intermediary elements between the digital signal inputs and the final analog output. These intermediaries actively compensate for offset voltages through their differential operation, isolating the final output from the detrimental effects of transistor offsets while maintaining a relatively simple circuit structure.
Data Source
AI summary
A semiconductor device having a novel structure is provided. Fluctuation in the grayscale voltage due to an offset voltage is suppressed. When a current corresponding to a lower-bit grayscale voltage is generated in a transconductance amplifier, voltages VHI and VLO supplied to the transconductance amplifier are alternately input to two input terminals in accordance with a digital signal of the most significant bit of lower bits. Since a change corresponding to the offset voltage is added to both the maximum and minimum values of the current output from the transconductance amplifier, fluctuation in the grayscale voltage due to the offset voltage can be suppressed.