Semiconductor Device Power Noise Reduction via Impedance Circuit
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Solution Overview
Problem
Semiconductor devices face challenges in reducing power voltage noise, as increasing the number of terminals to decrease inductance leads to larger package sizes and shifts the resonant frequency beyond operational limits, failing to effectively reduce impedance at the resonant frequency.
Innovation Solution
Incorporating an impedance circuit and an AC component interrupter between DC and AC power voltage terminals, and between DC and AC ground voltage terminals, to manage the AC and DC components separately, and using on-die capacitors and adjustable inductors to align parallel and serial resonant frequencies, thereby reducing power voltage noise without increasing impedance or dropping voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the number of power voltage terminals and ground voltage terminals is increased to reduce inductance, then power voltage noise is reduced, but package size increases
Solution Approach 1:
An impedance circuit is introduced as an intermediary component between the power voltage terminal and ground voltage terminal. This circuit includes a capacitor and inductor that create a resonant circuit to cancel out the inductive reactance of package interconnects, thereby reducing power voltage noise without requiring an increase in the number of terminals or package size.
Solution Approach 2:
The impedance circuit changes the electrical parameters (impedance characteristics) of the power delivery network by introducing reactive components with specific values. The capacitor and inductor are designed with particular L and C values to achieve resonance at the operating frequency, transforming the overall impedance profile to minimize noise while maintaining compact packaging.
2Object-affected harmful factors
If the number of power voltage terminals and ground voltage terminals is increased to reduce inductance, then power voltage noise is reduced, but resonant frequency shifts beyond operational limits
Solution Approach 1:
The impedance circuit acts as a mediator that introduces a controlled resonant frequency through its L-C components. This resonant circuit is designed to operate at the desired operational frequency, preventing the resonant frequency from shifting beyond operational limits while effectively reducing power voltage noise through impedance cancellation.
3Object-affected harmful factors
If impedance is reduced by increasing terminal count, then power voltage noise decreases, but device complexity increases
Solution Approach 1:
Instead of increasing terminal count, the patent uses an impedance circuit as a mediator that achieves noise reduction through electrical parameter optimization. This approach maintains the same terminal configuration while introducing reactive components that cancel inductive effects, thereby reducing noise without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces AC component power voltage noise while preventing an increase in DC component noise, maintaining impedance and voltage levels, and aligning resonant frequencies to minimize power voltage noise across semiconductor devices and printed circuit boards.
Implementation Method 1
an AC component interrupter connected between the AC component second power voltage terminal and ground and interrupting an AC component of power voltage
Implementation Method 2
A parallel resonant impedance Zp of the circuit illustrated in FIG. 2 is defined by Equation 1... A resonant frequency obtained using Equation 1 is... Power voltage noise Vn increases as electrical current I increases, and power voltage noise Vn has a maximum level at the resonant frequency
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a chip having a plurality of first power voltage terminals connected in common to a first power voltage line, a plurality of second power voltage terminals connected in common with a second power voltage line, a first connection terminal, a second connection terminal connected to the first power voltage line or the second power voltage line, and an on-die capacitor. The semiconductor device also includes a package having a plurality of third power voltage terminals connected to the first power voltage terminals through a first wire by wire bonding during a packaging process and a plurality of fourth power voltage terminals connected to the second power voltage terminals through a second wire by wire bonding during the packaging process, and configured to package the chip, wherein one end of the on-die capacitor is connected to the first connection terminal, and the first connection terminal is connected to the second connection terminal through a third wire by wire bonding during the packaging process.