Semiconductor Opening Patterning With Resist Platform and Blocking Layer

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Solution Overview

Problem

The challenge of reducing leakage and improving process yield in highly integrated semiconductor structures, such as DRAM, is exacerbated by the shrinking size and increased difficulty in manufacturing due to close component distances.

Innovation Solution

A method involving the use of a resist platform layer and a photoresist layer on a substrate, with specific etching processes to form openings, ensuring precise control through a boundary rule and selective etching of layers to create interconnect structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pitch between semiconductor structures is shortened to improve integration and performance, then the device density and performance are improved, but the leakage between components increases and manufacturing difficulty increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidcomponent leakage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the etching process into multiple stages with different photoresist layers (first photoresist layer and second photoresist layer) and corresponding etching processes (first etching process and second etching process). This segmentation allows precise control over the formation of openings at different depth levels, enabling shorter pitch structures while maintaining adequate isolation to prevent leakage between closely spaced components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension solution by forming a mandrel structure that extends through multiple layers, with openings formed at different depths (first openings and second openings). This three-dimensional approach to pattern formation allows achieving high-density lateral integration while maintaining vertical separation and control, thereby preventing leakage in closely spaced structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the size of semiconductor structures is shrunk to improve integration, then the device density is improved, but the manufacturing precision required increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidopening dimension control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the photoresist system into multiple layers (first photoresist layer and second photoresist layer) with different thicknesses and material properties. The first photoresist layer has greater thickness and forms first openings, while the second photoresist layer forms second openings. This segmentation enables independent optimization of each layer's dimensions and etching parameters, achieving precise control over opening sizes in shrunk structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes multiple parameters including photoresist material composition, layer thickness, etching selectivity ratios, and etching depth to achieve precise dimensional control. By adjusting these parameters across different etching stages, the patent enables accurate formation of small-scale openings required for high-density integration while maintaining manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If a single photoresist layer is used for etching, then the process is simple, but the precision and control over opening dimensions are insufficient

Engineering Contradiction:
Improveetching process simplicityVSAvoidopening dimension control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the single photoresist layer into multiple distinct photoresist layers, each with specific functions. The first photoresist layer is optimized for forming larger first openings with appropriate etching selectivity, while the second photoresist layer is optimized for forming smaller second openings. This segmentation maintains manufacturing feasibility while dramatically improving dimensional control and precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a mandrel structure as an intermediary element that facilitates precise opening formation. The mandrel serves as a template around which openings are formed, providing geometric control and enabling accurate dimensioning of the final openings. This intermediary approach bridges the gap between simple process steps and precise dimensional outcomes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances CD resolution and etching resistance, improving the yield and process window for semiconductor manufacturing by maintaining precise control over opening dimensions and reducing leakage.

Implementation Method 1

A reticle layer containing a hole pattern is formed on the photoresist layer by a lithography process

Methodology Applied
Scientific EffectPhotolithography: Photography

Implementation Method 2

The photoresist layer is etched until exposing the plurality of top surfaces of the blocking layer

Methodology Applied
Scientific EffectEtching:

Implementation Method 3

A blocking layer is deposited on the resist platform layer conformally

Methodology Applied
Scientific EffectConformal deposition: Physical Vapour Deposition

Data Source

PatentUS20250316492A1Method of manufacturing semiconductor structure
Publication Date: 2025.10.09 NAN YA TECH
  • US20250316492A1 patent drawing
  • US20250316492A1 patent drawing
  • US20250316492A1 patent drawing

AI summary

Embodiments of this disclosure provide a method of manufacturing a semiconductor structure, including the following steps. A substrate with an active device layer on the substrate is provided. A stack film layer on the active device layer is formed. A resist platform layer on the stack film layer is formed. A blocking layer is deposited on the resist platform layer conformally. A photoresist layer is formed on the blocking layer, and a top surface of the photoresist layer is higher than a topmost surface of the blocking layer. The resist platform layer is etched until exposing top surfaces of the blocking layer to form first openings. The blocking layer, the resist platform layer and the stack film layer are etched based on first openings until exposing top surfaces of the active device layer to form second openings.