Semiconductor Operation Circuits for Matrix Product Speed
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in matrix product calculations, particularly in deep neural networks, where accuracy requirements vary and traditional parallel processing methods are not optimized for power reduction and calculation speed enhancement.
Innovation Solution
A semiconductor device with product-sum operation circuitry comprising multiple arithmetic operators arranged in arrays, where common input values are shared among operators, reducing data transfers and enabling efficient parallel processing through shared data lines and post-processing using a lookup table for coefficient and index settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional parallel processing methods are used for matrix product calculations, then calculation speed can be improved, but data transfer overhead and circuit size increase
Solution Approach 1:
Multiple operation circuits share common first input terminals and common second input terminals, merging data paths to reduce redundant data transfers. This allows parallel calculation while minimizing the energy overhead associated with data movement across the circuit.
Solution Approach 2:
The operation circuits are designed with universal input terminals that can serve multiple circuits simultaneously. The first input terminals and second input terminals function as shared resources across groups of circuits, enabling the same physical infrastructure to support multiple parallel operations without proportionally increasing data transfer overhead.
2Productivity
If multiple arithmetic operators are used for parallel processing, then productivity is improved, but device complexity increases
Solution Approach 1:
Operation circuits are grouped such that multiple circuits share common input terminals. This merging approach allows parallel processing throughput to increase while the growth in device complexity is suppressed, as the number of unique input terminals grows more slowly than the number of operation circuits.
Solution Approach 2:
The parallel processing system is segmented into multiple groups of operation circuits, where each group shares common input terminals. This segmentation enables scalable parallel processing - productivity increases by adding more groups, while device complexity is managed by keeping each group's configuration relatively simple and uniform.
3Measurement precision
If accuracy requirements are increased for matrix product calculations, then calculation precision is improved, but processing time and power consumption increase
Solution Approach 1:
The patent applies different precision levels to different parts of the calculation process. By using fixed-point arithmetic with carefully selected bit allocations for integer and fractional parts, the system achieves sufficient accuracy for deep neural network operations while maintaining high processing speed. The accumulator uses enough bits to prevent overflow during accumulation while not excessive precision that would slow down computation.
Data Source
AI summary
According to an embodiment, there is provided a semiconductor device including a plurality of operation circuits each including a multiplier including a first input terminal and a second input terminal and configured to calculate a product of a value input via the first input terminal and a value input via the second input terminal, and an accumulator configured to integrate an output of the multiplier and output an integrated value that is obtained by integrating output values of the multiplier. The plurality of operation circuits are divided into groups by two manners, where by the first manner multiple operation circuits are configured to receive a common first value via the respective first input terminals, and by the second manner multiple operation circuits are configured to receive a common second value via the respective second input terminals.


