Semiconductor Device Operation Method for Reducing Arithmetic Variation
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Solution Overview
Problem
Hierarchical neural networks in semiconductor devices experience variations in arithmetic operation results, leading to low accuracy rates in inference and inefficient use of circuit area, especially during small-scale calculations.
Innovation Solution
An operation method for a semiconductor device that includes error obtaining, correction, and inference steps, utilizing multiple cell arrays and circuits to refine weight coefficients and input data, reducing variations and enhancing arithmetic efficiency per area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hierarchical neural networks with multiple layers and neurons are used, then processing capability is improved, but variation in arithmetic operation results increases
Solution Approach 1:
The patent applies preliminary action by performing correction operations before the main inference process. Specifically, it calculates correction values based on reference data and weight coefficients in advance, then applies these corrections to reduce variations in the final arithmetic operations. This pre-correction mechanism addresses the variation problem before it affects the main processing capability.
Solution Approach 2:
The patent implements feedback by using the results of reference arithmetic operations to generate correction values that are fed back into the system. The correction values are calculated based on the differences observed in reference operations and are then applied to subsequent operations to reduce variations. This feedback loop continuously improves the reliability of arithmetic operations while maintaining processing capability.
2Area of stationary object
If circuit area is reduced for compact design, then device size is improved, but arithmetic efficiency per area deteriorates
Solution Approach 1:
The patent applies universality by designing the cell array structure to perform multiple functions. The same cell array is used for both reference operations (to calculate correction values) and main inference operations. This multi-functional usage maximizes the utilization of the circuit area, ensuring that the reduced area does not compromise arithmetic efficiency per area.
Solution Approach 2:
The patent changes operational parameters by dynamically adjusting the use of correction values based on the specific inference task. The correction values are applied selectively to optimize the balance between circuit area utilization and arithmetic efficiency. This parameter adjustment allows the system to maintain high arithmetic efficiency per area even with a compact circuit design.
3Device complexity
If analog currents are used for arithmetic operations, then circuit scale is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent uses feedback to compensate for the lower measurement precision of analog currents. By performing reference operations and calculating correction values based on observed variations, the system feeds back corrective information that compensates for the inherent imprecision of analog arithmetic. This feedback mechanism maintains accuracy despite the use of simpler analog circuitry.
Solution Approach 2:
The patent applies copying by creating reference copies of arithmetic operations using the same analog circuitry. These reference operations are used to establish baseline values and correction factors that are then applied to main operations. The copying approach allows the system to maintain precision through comparison and correction while using compact analog circuits for all operations.
Data Source
AI summary
To provide an operation method of a semiconductor device in which a variation in arithmetic operation results is reduced. The semiconductor device includes first and second cell arrays and first to fifth circuits. First, third standard data is written from the fourth circuit to the second cell array, and first standard data is written from the first circuit to the first cell array. Then, second standard data is transmitted from the second circuit to the first cell array, a result of a product-sum operation of the first standard data and the second standard data is input from the first cell array to the third circuit, and fourth standard data corresponding to the result of the product-sum operation is transmitted from the third circuit to the second cell array. A result of a product-sum operation of the third standard data and the fourth standard data is input from the second cell array to the fifth circuit, and an output value corresponding to the result of the product-sum operation is output from the fifth circuit. Correction data corresponding to the difference between the output value and an expected value is retained in an empty cell of the first cell array and correction coefficients of the first and second cell arrays are calculated.