Semiconductor Device Integrating Optical and Electrical Elements on Single Substrate

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Solution Overview

Problem

Conventional methods for manufacturing semiconductor devices with integrated optical and electrical elements are costly due to the assembly of separate semiconductor chips, leading to high manufacturing costs.

Innovation Solution

A semiconductor device is fabricated with a substrate having distinct regions for optical and electrical elements, where the optical element is formed in one region with a stack of a semiconductor substrate, insulating layers, and semiconductor layers, and the electrical element is formed in another region with a similar stack, allowing for both elements to be integrated on a single substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If optical elements and electrical elements are formed on separate semiconductor chips and then assembled, then the device can be manufactured using conventional processes, but the manufacturing cost increases due to assembly costs

Engineering Contradiction:
Improvemanufacturing process compatibilityVSAvoidmanufacturing cost
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent merges the formation of optical elements and electrical elements onto a single semiconductor substrate. The substrate includes a first region with an optical element and a second region with an electrical element, both formed through integrated processing steps on the same substrate rather than assembling separate chips. This eliminates assembly costs while maintaining manufacturing compatibility.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor substrate serves multiple functions by accommodating both optical elements (waveguides, modulators, detectors) and electrical elements (transistors, interconnects) on the same platform. This multi-functional substrate design allows a single manufacturing process to produce both types of components, reducing overall manufacturing cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If optical elements and electrical elements are integrated on a single substrate, then manufacturing cost decreases by eliminating assembly, but the device complexity increases due to multiple regions and layers

Engineering Contradiction:
Improvemanufacturing costVSAvoidsubstrate structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The substrate is segmented into distinct functional regions: a first region for optical elements and a second region for electrical elements. Each region has its own optimized structure (e.g., waveguide layers in the first region, transistor layers in the second region), allowing complex functionality to be managed through spatial segmentation rather than uniform complexity throughout.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent manages complexity by organizing different element types in different spatial dimensions on the substrate. Optical elements are positioned in a first region with optical-specific layers, while electrical elements are positioned in a second region with electronic-specific layers, effectively using planar dimensionality to separate complex functions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11322668B2Semiconductor device
Publication Date: 2022.05.03 RENESAS ELECTRONICS CORP
  • US11322668B2 patent drawing
  • US11322668B2 patent drawing
  • US11322668B2 patent drawing

AI summary

A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.