Semiconductor Optical Receiver With Vertical Electrodes
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Solution Overview
Problem
Existing semiconductor optical receiver devices face a trade-off between reducing parasitic capacitance to improve response speed and maintaining light receiving sensitivity, as decreasing the diameter of the light receiving portion compromises optical coupling tolerance with optical fibers.
Innovation Solution
A semiconductor optical receiver device with a mesa structure where the inner diameter of the second contact layer is larger than or equal to the outer diameter of the first mesa, and a buried layer is formed to reduce parasitic capacitance while maintaining or enhancing light receiving sensitivity, achieved through specific layer formations and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the diameter of the light receiving portion is reduced to reduce parasitic capacitance, then response speed is improved, but light receiving sensitivity deteriorates
Solution Approach 1:
The patent transitions from a conventional planar electrode layout to a three-dimensional stacked configuration. The first electrode is positioned on the light receiving surface while the second electrode is placed on the back surface of the semiconductor substrate, creating a vertical electric field that passes through the light receiving portion. This dimensional change allows the light receiving area to be enlarged without increasing parasitic capacitance, as the electrode separation occurs in the depth direction rather than laterally.
Solution Approach 2:
The patent divides the electrode structure into two separate components located at different positions: the first electrode on the front surface and the second electrode on the back surface. This segmentation allows independent optimization of each electrode's function - the first electrode collects signal from the light receiving portion while the second electrode provides reference potential, thereby reducing parasitic capacitance between electrodes while maintaining adequate light receiving area.
2Speed
If the diameter of the light receiving portion is reduced to reduce parasitic capacitance, then response speed is improved, but optical coupling tolerance with optical fibers deteriorates
Solution Approach 1:
By positioning electrodes on opposite surfaces of the substrate, the patent creates a vertical electric field configuration that decouples the horizontal dimensions available for light receiving area from the capacitance-determining electrode separation distance. This enables the light receiving portion diameter to be increased for better optical coupling tolerance without proportionally increasing parasitic capacitance.
3Speed
If the outer diameter of the mirror is reduced to reduce parasitic capacitance, then response speed is improved, but light receiving sensitivity deteriorates
Solution Approach 1:
The patent eliminates the need for lateral electrode expansion by moving one electrode to the back surface. This vertical configuration removes the trade-off between mirror size and capacitance, allowing the mirror to be optimized for light receiving sensitivity without being constrained by parasitic capacitance considerations that would limit its diameter.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced parasitic capacitance without deteriorating light receiving sensitivity, enhancing response speed and facilitating optical fiber coupling, particularly in high-speed optical communication systems.
Implementation Method 1
a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer
Implementation Method 2
a buried layer in which the mesa is buried and the electric field is applied to the pn junction through the first and second contact layers
Data Source
AI summary
A semiconductor optical receiver device is provided, which a mesa comprising a plurality of semiconductor crystal layers formed on a semiconductor substrate including a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer and including a first contact layer on the semiconductor substrate, a plurality of electrodes to apply electric field to the pn junction are coupled on the semiconductor substrate, a second contact layer is formed on a buried layer in which the mesa is buried, and the electric field is applied to the pn junction through the first and second contact layers.