Semiconductor Device Attenuating High-Frequency Oscillation
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Solution Overview
Problem
Semiconductor devices with parallel-connected chips experience malfunctions due to high-frequency oscillations caused by parasitic inductance, which can exceed gate breakdown voltages or main electrode breakdown voltages, leading to malfunction.
Innovation Solution
The semiconductor device incorporates a resistance and inductance component in the paths between chips, added through a third electrode plate and wiring lines, to attenuate oscillations and adjust resonance frequency, preventing malfunctions by reducing oscillation amplitude and accelerating attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parasitic inductance of bonding wire is reduced to suppress oscillation, then oscillation suppression is improved, but high-frequency oscillation may be generated
Solution Approach 1:
The patent changes the electrical parameters of the bonding wire by controlling its diameter within a specific range (5μm to 10μm). This parameter adjustment optimizes the balance between parasitic inductance and high-frequency oscillation generation, allowing the system to suppress oscillation while avoiding the generation of harmful high-frequency oscillations.
2Object-affected harmful factors
If bonding wire diameter is increased to reduce high-frequency oscillation, then high-frequency oscillation is reduced, but parasitic inductance increases
Solution Approach 1:
The patent precisely controls the bonding wire diameter within the range of 5μm to 10μm to achieve optimal parameter balance. This parameter optimization ensures that the bonding wire has sufficiently low parasitic inductance for oscillation suppression while keeping high-frequency oscillation generation minimal.
3Power
If voltage exceeds gate breakdown voltage or main electrode breakdown voltage, then electrical performance is improved, but malfunction occurs
Solution Approach 1:
The patent applies preliminary anti-action by designing the bonding wire with optimized diameter before voltage application occurs. This pre-optimized structure prevents excessive voltage spikes and oscillations that could lead to breakdown, thereby protecting the device from malfunction when high voltages are applied.
Solution Approach 2:
The patent converts the potentially harmful effect of voltage stress into a beneficial outcome by using the optimized bonding wire structure to control and utilize voltage distribution. The carefully designed wire diameter manages voltage spikes and oscillations, transforming what could be damaging voltage exceedance into safe operational conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses malfunctions by reducing oscillation amplitude and adjusting resonance frequency, ensuring the semiconductor device operates within safe voltage limits.
Implementation Method 1
The semiconductor device includes a resistance and inductance component having a resistance value and an inductance value
Implementation Method 2
a frequency ω satisfying a resonance condition is represented as ω=(LC)−1/2 (L and C represent the inductance and the capacitance of the semiconductor device, respectively)
Data Source
AI summary
According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate.