Semiconductor Output Buffer Voltage Segmentation
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Solution Overview
Problem
The semiconductor device's latency counter experiences a decline in latch margin due to changes in external voltage, leading to potential failures in accepting internal read commands, as the phase difference between internal and input gate signals affects the timing synchronization.
Innovation Solution
The semiconductor device incorporates an output unit with a level shifter and impedance adjustment circuits, operating on different power supply voltages, to maintain accurate internal clock signals and stabilize the latency counter's operation despite external voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the internal voltage is used to operate the latency counter and other circuits, then power consumption is reduced, but the latch margin of the latency counter decreases when external voltage changes
Solution Approach 1:
The patent divides the voltage supply system into two independent segments: external voltage VDD supplies the DLL circuit and clock input circuit, while internal voltage VPERI supplies the latency counter and other peripheral circuits. This segmentation isolates the internal circuits from external voltage fluctuations, maintaining stable latch margins while keeping power consumption low through the use of lower internal voltage.
Solution Approach 2:
The patent introduces an intermediary approach by having the DLL circuit (operating on external voltage) generate stable internal clock signals that are then used by the latency counter (operating on internal voltage). The DLL circuit acts as a mediator that translates external voltage-dependent clock signals into stable internal clock signals, ensuring the latency counter maintains reliable operation despite using lower internal voltage.
2Adaptability or versatility
If circuits operating on external voltage are removed from the DLL circuit, then power consumption is reduced and external voltage independence is achieved, but phase synchronization may be affected
Solution Approach 1:
The patent segments the voltage supply responsibilities: the DLL circuit operates exclusively on internal voltage VPERI without external voltage-dependent circuits, achieving power efficiency and external voltage independence. Meanwhile, the clock input circuit operates on external voltage VDD to maintain phase synchronization with external clocks. This segmentation allows each circuit to operate optimally within its voltage domain.
Solution Approach 2:
The patent employs feedback mechanisms in the DLL circuit to maintain phase synchronization between internal and external clocks. The DLL circuit adjusts its internal clock phase based on feedback from phase detection circuits, ensuring that even though it operates on internal voltage, it remains synchronized with external clock signals, thus maintaining reliability without external voltage dependence.
Data Source
AI summary
The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.