Semiconductor Output Circuit Calibration for Parallel Impedance Precision
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Solution Overview
Problem
The existing methods for achieving high impedance precision in output circuits of semiconductor devices, which require adjustable output impedance, face significant errors when using multiple unit buffers in parallel due to power source resistance variations.
Innovation Solution
The output circuit employs a configuration where multiple unit buffers with the same transistor ON resistance values but different resistor values are connected in parallel, allowing for precise impedance adjustment by offsetting power source resistance deviations, thereby maintaining desired impedance accuracy even with increased buffer numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple unit buffers are used in parallel to achieve changeable output impedance, then the adaptability of output impedance is improved, but the measurement precision of output impedance deteriorates due to power source resistance variations
Solution Approach 1:
The patent applies local quality by giving different resistance values to resistors in different unit buffers. Specifically, unit buffers are divided into groups with different resistor values (e.g., first group with resistance R1, second group with resistance R2). This local differentiation allows the calibration circuit to compensate for power source resistance effects by selecting appropriate unit buffer groups, thereby maintaining impedance precision while preserving adaptability.
2Productivity
If multiple unit buffers are used in parallel to reduce output impedance, then the productivity of data transfer is improved, but the measurement precision of output impedance deteriorates due to increased error from power source resistance
Solution Approach 1:
The patent applies parameter changes by varying the resistor values in different unit buffers. Unit buffers are designed with different resistance parameters (R1, R2, etc.) so that when multiple buffers are used in parallel, the calibration circuit can select combinations that compensate for power source resistance effects. This allows the system to achieve both low output impedance (for high-speed data transfer) and high precision by appropriately selecting and calibrating the unit buffer configuration.
Data Source
AI summary
An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.