Semiconductor Device Output Timing Synchronization
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Solution Overview
Problem
In semiconductor devices like DRAM, matching the output timing of user data with the output timing of setting parameters read from a mode register is challenging due to different transmission paths for read commands and mode-register read commands, leading to synchronization issues and unnecessary power consumption.
Innovation Solution
The semiconductor device incorporates delay circuits that synchronize the timing signals for read and mode-register read operations, ensuring that the output timing of read data and setting parameters align, and prevents unnecessary power consumption by activating specific timing signals only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate transmission paths are used for read commands and mode-register read commands, then the device can handle different types of reads independently, but the output timing of user data and setting parameters cannot be easily synchronized
Solution Approach 1:
The patent merges the separate transmission paths by routing both user data and setting parameters through a common output buffer and data bus. The selection between setting parameters and user data is controlled by a selection signal that switches the data source, while both types of data share the same output timing control mechanism, thereby achieving synchronized output timing while maintaining independent handling capabilities.
2Loss of time
If timing signals are continuously activated to ensure synchronized output, then output timing alignment is achieved, but power consumption increases
Solution Approach 1:
The patent implements periodic activation of timing signals based on the type of read command received. The timing signal is activated only when a mode-register read command is detected, and remains inactive during regular read operations. This periodic activation pattern maintains output timing alignment when needed while minimizing power consumption by avoiding continuous signal activation.
3Loss of time
If the same transmission path is used for both setting parameters and user data, then output timing can be synchronized, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent implements a universal output buffer and data bus that can handle both setting parameters and user data. A single selection signal controls the data source, switching between setting parameters from the mode register and user data from the memory cell array. This multi-functional approach achieves timing synchronization while minimizing additional control complexity by using a shared infrastructure.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.