Semiconductor Output Wire Asymmetry for Inductance Reduction
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Solution Overview
Problem
Semiconductor devices with parallel output wires experience significant mutual inductance variations, leading to phase differences and waveform deterioration due to varying inductance between wires, particularly affecting high-frequency signal amplification.
Innovation Solution
The semiconductor device design features output wires with non-parallel arrangements and longer lengths than input wires, reducing mutual inductance by configuring adjacent output wires at specific angles (45° to 55°) and using dielectric substrates with capacitance components for impedance matching, thereby minimizing inductance variation and phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If output wires are arranged parallel to each other, then the layout is simple and easy to manufacture, but mutual inductance variations occur leading to phase differences and waveform deterioration
Solution Approach 1:
The patent applies asymmetry by arranging output wires in a non-parallel configuration with specific angles (45° to 55°) between adjacent wires. This asymmetric arrangement reduces mutual inductance variations between wires while maintaining manufacturing feasibility, thereby resolving the contradiction between layout simplicity and signal quality.
Solution Approach 2:
The patent changes the geometric parameters of wire arrangement by specifying particular angle ranges (45° to 55°) between adjacent output wires. This parameter optimization reduces mutual inductance effects while keeping the design manufacturable, addressing both ease of manufacture and reliability concerns.
2Reliability
If output wires are made longer to reduce inductance variation, then mutual inductance is reduced, but the circuit substrate area increases
Solution Approach 1:
The non-parallel arrangement with specific angles allows wires to achieve reduced mutual inductance without requiring excessive length, as the angular separation naturally decreases coupling effects. This resolves the contradiction by achieving inductance uniformity within a compact area.
Solution Approach 2:
The patent transitions from a two-dimensional parallel wire layout to a three-dimensional angular arrangement, utilizing spatial orientation to reduce mutual inductance. This dimensional change allows for reduced inductance variation without proportionally increasing the substrate area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces mutual inductance and inductance variation between output wires, enhancing the waveform quality and amplification of high-frequency signals, and allows for the miniaturization of circuit substrates.
Implementation Method 1
Semiconductor devices with parallel output wires experience significant mutual inductance variations, leading to phase differences and waveform deterioration
Implementation Method 2
using dielectric substrates with capacitance components for impedance matching, thereby minimizing inductance variation and phase differences
Data Source
AI summary
A semiconductor device includes at least one transistor, a plurality of input wires, and a plurality of output wires. The at least one transistor has a plurality of input pads arranged along one side of the at least one transistor and a plurality of output pads arranged along another side of the at least one transistor facing the one side. The plurality of input wires are respectively connected to the plurality of input pads. The plurality of output wires are respectively connected to the plurality of output pads and have longer wire lengths than the plurality of input wires. Adjacent input wires of the plurality of input wires are arranged parallel to each other, and adjacent output wires of the plurality of output wires are arranged non-parallel to each other.