Overcurrent Protection Device for Semiconductor with Mode-Based Timing Adjustment

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Solution Overview

Problem

Conventional overcurrent protection systems for semiconductor devices, particularly during regular ON time, face challenges in timely response and false detection prevention, with existing solutions requiring adjustments to gate threshold voltages and time lags, which are cumbersome and lack adequate prevention for regular ON time.

Innovation Solution

An overcurrent protection device that includes a current detection unit, an overcurrent detection unit, a mode determination unit, and a timing adjustment unit to accurately detect overcurrents and prevent false detections during turn-on and turn-off times without altering the gate threshold voltage settings, using a filter circuit to adjust detection timing based on mode determination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a false overcurrent detection prevention period is set to prevent false detection during turn-on and turn-off times, then false detection is prevented, but overcurrent detection during regular ON time is delayed

Engineering Contradiction:
Improvefalse detection preventionVSAvoidovercurrent detection response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the detection timing adjustable based on operational mode. The detection start timing is dynamically changed according to whether the semiconductor device is in turn-on time, turn-off time, or regular ON time, allowing the system to optimize between false detection prevention and rapid response based on the current operational state

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses preliminary action by determining the operational mode in advance and adjusting the detection timing accordingly. The mode determination unit identifies whether the device is in turn-on, turn-off, or regular ON time before overcurrent detection begins, allowing the timing adjustment unit to pre-set the appropriate detection start timing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If gate threshold voltage is adjusted to delay current rise in sense circuit, then false detection is prevented, but device complexity and adjustment difficulty increase

Engineering Contradiction:
Improvefalse detection preventionVSAvoidgate threshold voltage adjustment
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by adjusting the detection start timing parameter rather than the gate threshold voltage parameter. The timing adjustment unit modifies when detection begins based on operational mode, achieving false detection prevention through temporal parameter adjustment instead of voltage parameter adjustment

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediary approach by using a mode determination unit and timing adjustment unit that mediate between the sense circuit output and the overcurrent detection. Instead of directly adjusting the gate threshold voltage, the system uses these intermediary units to control detection timing based on operational state

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10770888B2Overcurrent protection device for semiconductor device
Publication Date: 2020.09.08 FUJI ELECTRIC CO LTD
  • US10770888B2 patent drawing
  • US10770888B2 patent drawing
  • US10770888B2 patent drawing

AI summary

The overcurrent protection device includes: a current detection unit configured to detect, as a sense voltage, a sense current flowing through a current sense terminal of a voltage-controlled semiconductor device; an overcurrent detection unit configured to compare the sense voltage detected by the current detection unit with an overcurrent threshold value to output an overcurrent detection signal; a mode determination unit configured to determine whether a superposition mode in which a transient sense voltage is superimposed on the sense voltage or a normal mode in which the transient sense voltage is not superimposed on the sense voltage; and a timing adjustment unit configured to adjust a detection start timing of the overcurrent detection signal based on a result of determination by the mode determination unit.