Semiconductor Device Overlap Region Threshold Voltage Control
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Solution Overview
Problem
Conventional semiconductor devices for controlling power face challenges in securing suitable threshold voltage characteristics while maintaining breakdown voltage characteristics, often requiring additional impurity implantation processes that increase production costs and time due to variations in impurity doping concentrations and gate insulation layer thicknesses.
Innovation Solution
The semiconductor device integrates transistors with different fabrication factors, such as impurity doping concentrations and gate insulation layer thicknesses, by forming overlap regions where the impurity region overlaps with the gate electrode or channel region, allowing for controlled threshold voltage adjustment without increasing production complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional impurity implantation processes are used to adjust threshold voltage, then threshold voltage characteristics are improved, but manufacturing complexity and production time increase
Solution Approach 1:
The patent forms the impurity region to overlap with the gate electrode or channel region before final transistor fabrication steps. This preliminary positioning of the impurity region enables subsequent threshold voltage adjustment through simple thermal processing or additional lightweight implantation steps, rather than requiring complex multi-step implantation processes at later stages.
Solution Approach 2:
The patent creates overlap regions where impurity concentration is locally increased in specific areas (where the impurity region overlaps with gate electrode or channel region). This localized impurity concentration adjustment allows precise control of threshold voltage in affected transistor regions without uniformly modifying the entire substrate, thereby simplifying the overall fabrication process.
2Manufacturing precision
If impurity doping concentration is increased to improve threshold voltage, then threshold voltage characteristics are improved, but breakdown voltage characteristics deteriorate
Solution Approach 1:
The patent forms overlap regions where impurity concentration is locally increased only in specific areas where the impurity region overlaps with the gate electrode or channel region. This localized approach allows threshold voltage adjustment in specific transistor regions without uniformly increasing impurity concentration across the entire substrate, thereby preserving breakdown voltage characteristics in regions where high impurity concentration is not needed.
Solution Approach 2:
The patent divides the substrate into different regions with different impurity concentrations - overlap regions with higher impurity concentration for threshold voltage control, and non-overlap regions with lower impurity concentration for maintaining breakdown voltage characteristics. This segmentation allows simultaneous optimization of both threshold voltage and breakdown voltage characteristics across different areas of the semiconductor device.
3Speed
If gate insulation layer thickness is reduced to improve transistor performance, then switching speed is improved, but breakdown voltage characteristics deteriorate
Solution Approach 1:
The patent creates overlap regions where impurity concentration is locally increased in areas where the impurity region overlaps with the gate electrode or channel region. This localized impurity enhancement compensates for the reduced gate insulation layer thickness, allowing thin gate insulation for fast switching while maintaining adequate breakdown voltage through the compensating impurity region.
Solution Approach 2:
The patent changes the impurity concentration parameter in overlap regions to compensate for the effects of reduced gate insulation layer thickness. By adjusting impurity concentration in specific areas, the patent enables the use of thinner gate insulation layers for improved switching speed while maintaining the necessary breakdown voltage characteristics through the compensating effect of the impurity region.
Data Source
AI summary
A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.