Semiconductor Overlapped PN Structure for Breakdown Voltage Control
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Solution Overview
Problem
Existing semiconductor device manufacturing processes are complex and costly due to the limited ability to adjust breakdown voltages without increasing the number of masks and ion implantation processes, as they require different diffusion regions for various devices on the same wafer.
Innovation Solution
A semiconductor overlapped PN structure with dual-implanted and single-implanted regions allows for flexible adjustment of breakdown voltages by varying the number, shape, size, or arrangement of dual-implanted regions without additional masks or ion implantation processes, using a substrate with P and N type wells and overlapping regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional masks and ion implantation processes are used to provide different breakdown voltages for different devices on the same wafer, then the breakdown voltage adjustability is improved, but the manufacturing process complexity and cost increase
Solution Approach 1:
The overlapped region is segmented into multiple dual-implanted regions, each with different ratios of P type to N type impurities. This segmentation allows different breakdown voltages to be achieved within the same overlapped region without requiring additional masks or implantation processes, as each dual-implanted region can be independently configured during the diffusion process.
Solution Approach 2:
Different dual-implanted regions within the overlapped region have different local impurity concentrations and ratios. By controlling the distribution and composition of P type and N type impurities in specific local areas, the patent achieves spatially varying breakdown voltages across different devices on the same wafer, eliminating the need for additional processing steps.
2Manufacturing precision
If the concentration of P type and N type impurities is adjusted to provide different breakdown voltages, then the breakdown voltage control is improved, but the manufacturing process becomes more complex requiring additional masks and ion implantation processes
Solution Approach 1:
The patent merges the formation of P type and N type impurity regions into a single diffusion process. By using dual-implanted regions that contain both P type and N type impurities, the patent combines what would traditionally require separate implantation steps into one unified process, achieving precise breakdown voltage control without increasing process complexity.
Solution Approach 2:
The patent changes the parameters of the diffusion process by controlling the ratio of P type to N type impurities in the dual-implanted regions. By adjusting these impurity ratios during a single diffusion process, the patent achieves precise control over breakdown voltages for different devices without requiring multiple implantation steps or additional masks.
3Device complexity
If separate P type well and N type well regions are used without overlap, then the manufacturing process is simpler, but the breakdown voltage adjustability is limited
Solution Approach 1:
The patent implements a nested structure where dual-implanted regions containing both P type and N type impurities are embedded within the overlapped region of P type and N type wells. This nesting allows the simple manufacturing process of separate well formation to be maintained while incorporating the versatility of adjustable breakdown voltages through the embedded dual-implanted regions with variable impurity ratios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of semiconductor devices with different breakdown voltages on the same wafer without increasing complexity or cost, by adjusting the ratio of P type to N type impurities through the definition of dual-implanted regions using a single mask, thereby simplifying the manufacturing process.
Implementation Method 1
During a diffusion process after the implantation process, ions of the P type well 11 and ions of the N type well 12 will diffuse toward each other to form a diffusion region 13 between the P type well 11 and the N type well 12
Implementation Method 2
it is often required for a semiconductor device to be implanted with P type impurities and N type impurities in a substrate
Data Source
AI summary
The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.