Semiconductor Device Patterning via Overlapping Lithography

The patent applies segmentation by dividing the single patterning process into multiple sequential photolithography and etching steps. Each step creates a subset of the final pattern, with intermediate patterns being formed and then combined. This segmentation allows each individual patterning step to work within achievable resolution limits while the cumulative effect achieves the required precision for smaller features that would be impossible with a single step.

The patent employs dimensionality change by using multiple photomasks with different orientations (e.g., first photomask for vertical lines, second photomask for horizontal lines). Instead of attempting to pattern all features in a single dimensional pass, the process distributes pattern formation across multiple dimensional approaches. This allows each photomask to focus on specific feature orientations, achieving the required overlay accuracy for decreased feature sizes by breaking down the complex 2D/3D patterning challenge into manageable directional components.

The patent applies merging by combining multiple photolithography and etching processes into an integrated multi-step workflow that achieves superior pattern resolution. Rather than using a single expensive high-resolution lithography step, the method merges several standard-resolution steps, each contributing part of the final pattern. This merging approach achieves the required manufacturing precision for densely packed devices while keeping individual process steps within cost-effective parameters, as each step uses conventional lithography equipment rather than pushing the limits of single-step resolution.