Semiconductor Electrode Layout With Overlapping Pads for Smaller Chips
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Solution Overview
Problem
Current semiconductor devices face design constraints due to the size and placement of electrodes, limiting the flexibility and efficiency of chip design, particularly in the arrangement of the main surface gate electrode and source electrode, which restricts the expansion of the active region and increases chip size and cost.
Innovation Solution
The semiconductor device incorporates a gate pad and source pad that overlap the main surface gate and source electrodes in plan view, allowing for a larger gate pad size and reducing the active region's size constraints, thereby relaxing design rules and enabling a more efficient use of the semiconductor layer for smaller and cost-effective designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate electrode and source electrode are arranged with standard spacing on the main surface, then electrical connection is ensured, but the active region expansion is restricted and chip size increases
Solution Approach 1:
The patent applies dimensionality change by extending the gate electrode and source electrode from the main surface to the back surface of the semiconductor substrate. This vertical extension into the third dimension allows the electrodes to maintain electrical connection while reducing their planar footprint on the main surface, thereby enabling active region expansion without increasing chip size.
Solution Approach 2:
The patent implements nesting by positioning the gate electrode and source electrode such that they overlap in the plan view when extending from main surface to back surface. The electrodes are nested within each other's projection area, allowing multiple electrode functions to occupy overlapping spatial volumes, which reduces the required chip area while maintaining electrical connectivity.
2Reliability
If the electrode size is increased to ensure proper electrical connection, then connection reliability is improved, but design flexibility is reduced and chip area increases
Solution Approach 1:
By extending electrodes vertically from main surface to back surface, the patent maintains robust electrical connection (improving reliability) while reducing the electrodes' horizontal footprint. This dimensional transition allows designers to maintain connection integrity without being constrained by large planar electrode dimensions, thereby improving design flexibility.
Solution Approach 2:
The overlapping arrangement of gate and source electrodes in plan view creates a nested configuration where electrodes share vertical space. This nesting maintains reliable electrical connections through sufficient conductor cross-section while reducing the overall chip area required, thus enhancing design flexibility without compromising connection reliability.
3Ease of manufacture
If the electrode arrangement follows conventional design rules, then manufacturing is simplified, but chip size and cost increase
Solution Approach 1:
The patent extends electrodes from main surface to back surface, utilizing the vertical dimension to reduce planar chip area. This approach maintains manufacturing simplicity by using standard electrode formation processes extended into the third dimension, while achieving smaller chip sizes and reduced costs.
Solution Approach 2:
The overlapping electrode arrangement in plan view creates a nested structure that reduces the total chip area required. This nesting configuration can be integrated into existing manufacturing processes with minimal modification, maintaining ease of manufacture while reducing chip size and associated costs.
Data Source
AI summary
The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.