Semiconductor Device With Overlapping Poly-Silicon Resistance

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Solution Overview

Problem

The dishing phenomenon during the CMP method for semiconductor device manufacturing hinders the miniaturization of semiconductor devices due to the difficulty in arranging dummy semiconductor layers below poly-silicon resistance elements, leading to increased parasitic capacitance and area occupation in element isolation regions.

Innovation Solution

Forming island-like semiconductor layers and a second insulation film to surround the first insulation film, allowing the poly-silicon resistance elements to be overlapped on the upper surface of the second semiconductor layer, which is structurally independent from the first semiconductor layer, thereby reducing the area of the element isolation region and minimizing the substrate bias effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a dummy semiconductor layer is formed in the element isolation region to suppress the dishing phenomenon during CMP, then the flatness of the wafer is improved, but the area of the element isolation region increases and device miniaturization is hindered

Engineering Contradiction:

Improveflatness of waferVSAvoidarea of element isolation region

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The invention changes the spatial arrangement from planar (side-by-side) to vertical (overlapping). The resistance element is positioned to overlap with the dummy semiconductor layer in the planar view, utilizing the vertical dimension to accommodate both structures without increasing the horizontal footprint of the element isolation region.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The resistance element is nested over the dummy semiconductor layer, with the dummy layer acting as a support structure beneath the resistance element. This nesting arrangement allows the resistance element to be positioned above the dummy layer, effectively using the same horizontal space for both structures.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Manufacturing precision

If a dummy semiconductor layer is formed to suppress dishing phenomenon, then CMP flatness is improved, but parasitic capacitance increases due to the additional structure

Engineering Contradiction:

ImproveCMP flatnessVSAvoidparasitic capacitance

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A third insulation film is introduced as an intermediary layer between the dummy semiconductor layer and the resistance element. This intermediate insulation layer electrically isolates the two conductive structures, preventing direct capacitive coupling and thereby reducing parasitic capacitance while still allowing the dummy layer to perform its dishing suppression function.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If the occupation ratio of semiconductor layer in each imaginary region is increased to 15-20% or more, then the dishing phenomenon is suppressed, but the element isolation region occupies more area

Engineering Contradiction:

Improvedishing suppressionVSAvoidelement isolation region area

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The invention utilizes the vertical overlapping dimension to increase the effective occupation ratio of the semiconductor layer without expanding the horizontal area of the element isolation region. By allowing the resistance element to overlap with the dummy semiconductor layer, the semiconductor content is increased in the vertical stack while maintaining compact horizontal dimensions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the miniaturization of semiconductor devices by reducing the area of the element isolation region and stabilizing the resistance element characteristics, while maintaining high accuracy and reducing parasitic capacitance.

Implementation Method 1

an insulation film formed of a silicon oxide film, for example is stacked on the main surface of the semiconductor substrate using a CVD (Chemical Vapour Deposition) method

Methodology Applied

Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Implementation Method 2

the insulation film formed over the main surface of the semiconductor substrate is removed using, for example, a CMP (Chemical Mechanical Polishing) method

Methodology Applied

Scientific EffectChemical Mechanical Polishing:

Data Source

PatentUS7898032B2Semiconductor device and a method of manufacturing the same

Publication Date: 2011.03.01 RENESAS ELECTRONICS CORP

AI summary

The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.