Semiconductor Overlapping Well Region for High Voltage Logic Integration
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Solution Overview
Problem
The integration of high voltage/power devices and low voltage logic devices on a single System-on-a-chip (SOC) is complex and costly, and existing methods struggle to enhance both breakdown voltage and device performance while reducing specific on-resistance due to the short drift region in extended drain metal oxide semiconductor (EDMOS) devices.
Innovation Solution
A semiconductor device design that incorporates a substrate with a first and second well region, an overlapping region with lower net doping concentration, a gate insulating layer, and a gate electrode, along with a source and drain region, where the overlapping region's net doping concentration decreases from the boundary between the first and second well regions, and an LDD region is used to improve electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drift region length is extremely short, then device performance (speed) is improved, but breakdown voltage cannot be raised
Solution Approach 1:
The patent applies local quality by creating an overlapping region with non-uniform doping concentration between the n-well and p-well. The doping concentration is designed to decrease from the n-well side toward the p-well side, creating a gradient that locally optimizes both breakdown voltage and device performance in different regions of the drift area.
Solution Approach 2:
The patent changes the doping concentration parameter by introducing an overlapping region where the net doping concentration decreases gradually from the n-well boundary to the p-well boundary. This parameter variation allows the drift region to maintain high breakdown voltage near the n-well while preserving fast switching performance in the channel region.
2Device complexity
If the drift region length is extremely short, then manufacturing complexity is reduced, but specific on-resistance cannot be lowered
Solution Approach 1:
The patent uses local quality by creating an overlapping region with spatially varying doping concentration. The doping profile is designed to have higher concentration near the n-well and lower concentration toward the p-well, which locally optimizes the electric field distribution to reduce specific on-resistance without requiring additional manufacturing steps.
Solution Approach 2:
The patent merges the n-well and p-well regions to create an overlapping region where both wells coexist. This merging eliminates the need for separate drift regions while achieving both low specific on-resistance and high breakdown voltage through the combined doping profiles of the two wells.
3Productivity
If high voltage/power devices and low voltage logic devices are integrated on a single chip, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by designing the overlapping region to serve multiple functions simultaneously: it acts as the drift region for high voltage/power devices while also serving as the channel region for low voltage logic devices. This multi-functionality allows both device types to be integrated on a single chip using a unified manufacturing process.
Solution Approach 2:
The patent merges high voltage and low voltage device structures into a single overlapping region, allowing both device types to share common manufacturing steps. The n-well and p-well regions are formed in the same process sequence, eliminating the need for separate fabrication lines and reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances device performance, breakdown voltage, and reduces specific on-resistance by optimizing the doping concentration and structure of the overlapping region, leading to improved electrical characteristics and current drivability.
Implementation Method 1
the length of drift region between the channel region and RESUEF (Reduced Surface Electric Field) STI (Shallow Trench Isolation)
Implementation Method 2
The first and the second well regions are relatively lightly doped by performing boron and indium dopant (the first well), and phosphorus and arsenic dopant (the second well) ion implantation
Data Source
AI summary
A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region. The semiconductor device may also include a separating unit, which is formed in the second well region on the drain side and may be formed as a shallow trench isolation (STI) region having a lower depth than the second well region.