Semiconductor Overlay Marks With Laser Scanning to Reduce Polymer Defects
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization, higher speed, greater bandwidth, lower power consumption, and latency, which require smaller and more creative packaging techniques for semiconductor dies, particularly in stacked and bonded semiconductor devices.
Innovation Solution
The solution involves a method of manufacturing semiconductor devices that includes forming through vias, attaching semiconductor devices to a carrier substrate with an adhesive layer and a polymer layer, and using a redistribution layer to interconnect the devices. Additionally, a marking process is used to create cross-free characters within the polymer layer for identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If repeated reductions in minimum feature size are implemented to improve integration density, then more components can be integrated into a given area, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar 2D integration to 3D stacked integration by bonding multiple semiconductor dies vertically. This dimensional change allows continued increase in integration density without further reducing feature sizes, thereby avoiding the associated manufacturing complexity and process node shrinkage challenges.
Solution Approach 2:
The patent implements a stacked device architecture where multiple semiconductor dies are bonded together in a vertical stack, with each die containing functional circuits. This nesting approach packs more computational resources into a smaller footprint by utilizing the third dimension, effectively increasing integration density without requiring smaller feature sizes.
2Volume of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then device footprint is reduced, but alignment precision requirements increase
Solution Approach 1:
The patent forms alignment marks and overlay structures on the semiconductor dies before the bonding process. These pre-formed marks serve as registration features that guide the bonding alignment, enabling precise stacking without requiring extremely tight process control during the bonding operation itself.
Solution Approach 2:
The patent introduces alignment marks and overlay structures as intermediary features that mediate the alignment between stacked dies. These marks act as reference features that simplify the bonding alignment process, allowing achieving the required precision without directly controlling all geometric parameters of the dies themselves.
3Manufacturing precision
If laser marking is used to create overlay marks, then alignment precision is improved, but defects may be introduced in the polymer layer
Solution Approach 1:
The patent modifies laser marking parameters including pulse duration, energy density, and scanning speed to optimize the marking process. By carefully controlling these parameters, the patent achieves sufficient alignment precision while minimizing thermal damage and defect formation in the polymer layer and underlying semiconductor structures.
Solution Approach 2:
The patent uses pulsed laser marking instead of continuous laser exposure. The periodic pulsing allows heat to dissipate between pulses, preventing excessive thermal accumulation that could cause defects. This periodic action maintains alignment precision while reducing the risk of thermal damage to the polymer layer and semiconductor devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more efficient semiconductor devices with improved thermal control and reduced defects, facilitating the integration of multiple semiconductor devices in a compact package-on-package structure.
Implementation Method 1
a marking process is used to create cross-free characters within the polymer layer for identification
Data Source
AI summary
A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.