Semiconductor Substrate Overlay Mark Arrangement
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Solution Overview
Problem
In semiconductor manufacturing, overlay errors between patterned layers occur due to alignment inaccuracies and wafer warpage, leading to measurement challenges as overlay marks in scribe lanes become closer, causing issues with overlay measurement precision.
Innovation Solution
The semiconductor substrate design arranges overlay marks within scribe lanes in a direction different from the adjacent exposure shot regions, increasing the distance between adjacent marks and improving measurement accuracy by positioning them in the peripheral parts of the exposure shot regions and placing the scribe lane between the center parts of these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of scribe lanes between different dies becomes smaller to obtain more effective dies area, then the productivity increases, but the overlay marks disposed in the scribe lanes become closer to one another causing measurement problems
Solution Approach 1:
The patent changes the arrangement dimension of overlay marks from the first direction (parallel to exposure shot regions) to the second direction (perpendicular or at an angle to exposure shot regions). This dimensional change allows overlay marks to be positioned in the peripheral parts of exposure shot regions while maintaining adequate spacing, thus resolving the measurement precision problem while preserving the reduced scribe lane size for higher productivity.
2Area of stationary object
If overlay marks are disposed in the scribe lane closer together to maximize dies area, then the productivity increases, but the overlay marks suffer from measurement problems due to being too close
Solution Approach 1:
The patent applies different spatial arrangements to different regions: overlay marks in the peripheral parts of exposure shot regions are arranged in the second direction (perpendicular to exposure shot regions), while the center parts contain the main circuit patterns. This local differentiation allows adequate spacing for peripheral marks without compromising the compact center region, thus maintaining both dies area and measurement precision.
3Measurement precision
If the distance between adjacent overlay marks in the scribe lane is increased to improve measurement accuracy, then the measurement precision improves, but the scribe lane size must increase reducing effective dies area
Solution Approach 1:
By arranging overlay marks in the second direction (perpendicular or at an angle to the first direction of exposure shot regions), the patent achieves adequate spacing between marks without increasing the scribe lane size in the first direction. This allows the scribe lane to remain compact, preserving effective dies area while ensuring measurement precision through proper mark spacing.
Data Source
AI summary
A semiconductor substrate includes a first exposure shot region, a second exposure shot region aligned with the first exposure shot region in a first direction, first overlay marks, second overlay marks, and a scribe lane. The first overlay marks are disposed in a first peripheral part of the first exposure shot region. The second overlay marks are disposed in a second peripheral part of the second exposure shot region. The scribe lane is disposed between a first center part of the first exposure shot region and a second center part of the second exposure shot region. A center point of the first overlay mark disposed within the scribe lane and a center point of the second overlay mark which is closest to the first overlay mark are arranged in a second direction different from the first direction for increasing the distance between the first and the second overlay marks.