Semiconductor Overlay Measurement Mark Using Vernier Scale Patterns

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Solution Overview

Problem

Conventional semiconductor device overlay measurement marks, such as box-type or frame-type, are limited in precision and size, leading to increased possibilities of defective devices due to imprecise overlay measurements, especially when pattern densities are high and feature sizes are below 70 nm, requiring a more precise and smaller overlay measurement mark for accurate positioning.

Innovation Solution

The introduction of line and space patterns in a scribe line region on a semiconductor substrate, with line-shaped vernier scale patterns having smaller widths than the main scale patterns, allowing for precise overlay measurement by calculating x-axis and y-axis overlays between the main scale and vernier scale patterns, reducing error and improving measurement reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional box-type or frame-type overlay measurement marks are used, then the measurement process is simple, but the measurement precision is insufficient for high-density patterns and sub-70nm features

Engineering Contradiction:

Improveoverlay measurement precisionVSAvoidmeasurement mark structure complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The measurement mark is segmented into distinct main scale patterns and vernier scale patterns with different line widths. The main scale has wider lines while the vernier scale has narrower lines, allowing differential measurement that achieves sub-70nm precision. This segmentation enables the measurement system to resolve finer overlay errors by comparing the relative positions of the two scale types.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the measurement mark have different local properties - the main scale patterns have larger line widths optimized for robust detection, while the vernier scale patterns have smaller line widths optimized for high-precision measurement. This local differentiation allows each region to serve its specific function while contributing to overall measurement accuracy.

Inventive Principle:

Principle #3Local quality

2Reliability

If conventional overlay measurement marks are used, then the manufacturing process is straightforward, but the measurement reliability increases the possibility of defective devices

Engineering Contradiction:

Improveoverlay measurement reliabilityVSAvoidmeasurement mark fabrication ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The main scale and vernier scale patterns are formed as separate structures during the lower pattern formation process, before the upper pattern is created. This preliminary formation allows the measurement mark to be established early in the fabrication sequence, enabling overlay verification to be performed on subsequent layers with higher reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The vernier scale patterns act as an intermediary reference that mediates between the main scale and the upper pattern being formed. By providing this intermediate measurement reference with different line width characteristics, the system achieves more reliable overlay measurement that reduces device defects.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If conventional overlay measurement marks are used, then the device structure is simple, but the measurement precision is insufficient for high integration density

Engineering Contradiction:

Improveoverlay measurement precisionVSAvoidmeasurement mark area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The measurement mark utilizes dimensional differentiation through varying line widths in the same planar space. By encoding measurement information in the width dimension rather than requiring larger spatial separation, the design achieves high measurement precision within a compact area suitable for high integration density devices.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7582899B2Semiconductor device having overlay measurement mark and method of fabricating the same

Publication Date: 2009.09.01 SAMSUNG ELECTRONICS CO LTD

AI summary

There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.