Semiconductor Overlay Pattern Segmentation for Alignment Precision
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in maintaining overlay consistency between layers, particularly as pattern sizes decrease, leading to misalignment issues and potential damage to overlay patterns due to loading effects during processing.
Innovation Solution
The implementation of a semiconductor device with a first diffraction-based overlay pattern and a second scanning electron microscope (SEM) overlay pattern, where the SEM pattern is placed in a forbidden region surrounding the diffraction-based pattern, allowing for precise measurement and feedback to reduce misalignment and loading effects, thereby enhancing overlay consistency and reducing pattern damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single overlay pattern is used for measurement, then the measurement process is simple, but the overlay consistency and measurement precision are insufficient
Solution Approach 1:
The overlay measurement system is segmented into two distinct patterns: a first overlay pattern for initial overlay measurement and a second overlay pattern for refined measurement. This segmentation allows each pattern to be optimized for its specific measurement function, improving overall overlay consistency while maintaining manageable complexity through clear functional division.
Solution Approach 2:
The second overlay pattern acts as an intermediary measurement tool that provides more precise overlay data without directly interfering with the primary circuit patterns. This intermediary pattern enables high-precision measurement while protecting the main device structures from measurement-related damage.
2Measurement precision
If overlay measurement is performed on existing patterns, then no additional patterns are needed, but the measurement process damages the overlay patterns due to loading effects
Solution Approach 1:
The measurement function is extracted from the primary circuit patterns and assigned to dedicated overlay patterns. The second overlay pattern is specifically designed and placed in the forbidden region to serve exclusively as a measurement target, thereby eliminating the loading effect damage that would occur if measurement were performed on functional circuit patterns.
Solution Approach 2:
The second overlay pattern functions as a disposable measurement target that can be deliberately damaged or removed after serving its measurement purpose. This dedicated pattern absorbs the measurement-related stress and damage, protecting the valuable circuit patterns while enabling precise overlay measurement.
3Area of moving object
If pattern size is decreased to increase device density, then device integration is improved, but overlay alignment becomes more difficult and misalignment increases
Solution Approach 1:
The solution introduces a spatial dimension separation by placing the second overlay pattern in the forbidden region, a specific spatial zone远离 from the primary circuit patterns. This dimensional separation allows high-precision measurement without interfering with the miniaturized circuit structures, enabling both high device density and high overlay alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves overlay consistency and enables full inspection of semiconductor devices using SEM, reducing defects and maintaining pattern integrity by utilizing the SEM pattern as a dedicated measurement tool without damaging the actual circuit patterns.
Implementation Method 1
The first overlay pattern may be a diffraction-based overlay (DBO) pattern
Implementation Method 2
the second overlay pattern may be a scanning electron microscope (SEM) overlay pattern
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.


