Semiconductor Overlay Vernier Step Error Elimination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, the step errors in the mother vernier formation lead to inaccuracies in the child vernier pattern, causing misalignment and measurement failures during the photo process.
Innovation Solution
A method is introduced where a mother vernier with a square frame shape and internal space is formed, followed by creating a child vernier pad within this space, allowing the child vernier to be formed without the step error, using an etch process, polishing, and photoresist coating to ensure accurate pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mother vernier is formed by etching trenches in the scribe region, then the mother vernier structure is created, but step errors are introduced that cause inaccuracies in child vernier pattern formation
Solution Approach 1:
The harmful step structure is extracted and removed by performing a polishing process after forming the insulating layer. This eliminates the step errors that would otherwise cause pattern formation inaccuracies, while preserving the mother vernier's alignment reference function.
Solution Approach 2:
An insulating layer is formed over the mother vernier before polishing. This preliminary action protects the mother vernier structure during the polishing process that removes the step, ensuring the mother vernier remains intact while eliminating the harmful steps.
2Reliability
If the mother vernier has a projected structure from the wafer surface, then it serves as an alignment reference, but it causes exposure process failures and misalignment in the child vernier formation
Solution Approach 1:
The projected mother vernier structure, which initially causes harm through step errors, is converted into a beneficial feature. The polishing process uses the mother vernier's material hardness or etch selectivity to selectively remove the insulating layer and steps while preserving the mother vernier itself, transforming the problematic structure into a precise alignment reference without steps.
3Manufacturing precision
If polishing is performed to expose the mother vernier top surface, then the step is removed, but additional process steps are required
Solution Approach 1:
The polishing step that removes the insulating layer and the step-flattening operation are merged into a single integrated process. This simultaneous achievement of both insulation removal and step elimination reduces the total number of separate process steps while maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents pattern failures and ensures accurate alignment measurements by eliminating step errors in the child vernier formation, enhancing the reliability of subsequent processes.
Implementation Method 1
trenches are formed in the scribe regions of a semiconductor substrate 10 by means of an etch process
Implementation Method 2
A polishing process is then performed to expose the top surface of the mother verniers 11
Implementation Method 3
Exposure and development processes are then performed on the inner sides of the mother vernier 11 to form a child vernier 13
Data Source
AI summary
After a mother vernier pattern is formed in a scribe region of a semiconductor substrate, a child vernier pad is formed on the inner region of a mother vernier, and a child vernier is formed on the child vernier pad in order to obviate the step of the mother vernier. Thus, at the time of an exposure process for forming the child vernier, failure of the pattern due to the step can be prevented and alignment can be measured accurately.