3D Semiconductor Memory via Oxidation Patterning
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Solution Overview
Problem
The integration density of conventional two-dimensional (2D) semiconductor memory devices is limited by the cost and complexity of forming fine patterns, while three-dimensional (3D) semiconductor devices are expensive and have reliability concerns.
Innovation Solution
A method involving the formation of a thin layer structure with alternately stacked insulating and gate layers on a substrate, through-holes are created, and oxidation processes are used to form patterns on the gate and substrate layers, followed by selective epitaxial growth to form semiconductor patterns, allowing for the formation of gate electrodes and vertical insulators, which simplifies the manufacturing process and enhances integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 2D memory devices use high-priced equipment to form fine patterns, then integration density can be improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive mechanical lithography equipment with a chemical self-organization system. Block copolymer films spontaneously form nanoscale patterns through phase separation, eliminating the need for costly lithography tools while achieving sub-10nm feature sizes. This chemical self-assembly approach directly resolves the contradiction by providing high precision patterning at low cost.
Solution Approach 2:
The patent changes the fundamental parameter of pattern formation from top-down lithographic writing to bottom-up chemical self-organization. By controlling block copolymer composition, film thickness, and annealing conditions, nanoscale patterns emerge automatically. This parameter transformation enables fine pattern formation without expensive equipment, directly addressing the cost-precision tradeoff.
2Productivity
If 3D semiconductor devices are produced, then integration density can be improved, but manufacturing cost and reliability concerns increase
Solution Approach 1:
The patent transitions from 2D planar memory architecture to 3D vertically stacked architecture. Multiple memory layers are stacked in the vertical dimension, dramatically increasing storage capacity per chip area. This dimensional transition directly improves integration density while the block copolymer patterning technique keeps manufacturing costs low, resolving the contradiction between 3D integration benefits and manufacturing challenges.
Solution Approach 2:
The patent divides the 3D memory structure into multiple discrete functional layers (tunnel insulator, charge trap layer, blocking insulator, semiconductor layers) that are sequentially formed. Each layer can be independently optimized and controlled, simplifying the manufacturing process despite the complex 3D architecture. This segmentation approach enables reliable 3D device production at lower costs.
3Ease of manufacture
If block copolymer films are used for patterning, then fine patterns can be formed at low cost, but pattern uniformity and control may be challenging
Solution Approach 1:
The patent employs self-consistent feedback mechanisms where the block copolymer system automatically adjusts its phase separation morphology based on film thickness, composition, and thermal history. The system finds its own equilibrium state, ensuring uniform pattern formation across the substrate. This intrinsic feedback control achieves high pattern uniformity without expensive external control equipment.
Solution Approach 2:
The patent performs preliminary optimization of block copolymer synthesis parameters, film deposition conditions, and annealing protocols before actual patterning. By pre-establishing optimal processing windows and material compositions, the system ensures consistent pattern uniformity across production batches. This preliminary preparation eliminates the need for expensive real-time control equipment during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of highly integrated 3D semiconductor memory devices with reduced manufacturing complexity and cost, while improving reliability and integration density.
Implementation Method 1
forming the first patterns may include oxidizing portions of the gate layers, and forming the second patterns may include oxidizing the portions of the substrate that are exposed by the through-holes
Implementation Method 2
forming the lower semiconductor patterns may include performing a selective epitaxial growth (SEG) process on portions of the substrate that are exposed by removing the second patterns
Data Source
AI summary
Methods of forming semiconductor devices are provided. A method of forming a semiconductor device may include forming a structure including insulating layers and gate layers that are alternately and repeatedly stacked on a substrate. The method may include forming through-holes in the structure. The method may include forming first patterns on sidewalls of the gate layers, by performing an oxidation process. The method may include forming second patterns on portions of the substrate, by performing the oxidation process. The method may include removing the second patterns. Moreover, the method may include forming semiconductor patterns in the through-holes.