Semiconductor Device Parasitic Capacitance Reduction via Oxide Insulating Layer
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Solution Overview
Problem
In semiconductor devices with thin film transistors, parasitic capacitance between wirings can lead to signal distortion, increased power consumption, and reduced display quality, especially in active matrix display devices and when miniaturizing circuits.
Innovation Solution
A semiconductor device structure is implemented where an oxide insulating layer is formed over the peripheral portion of the oxide semiconductor layer, increasing the distance between gate and wiring layers and reducing parasitic capacitance without increasing the number of manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the distance between gate and wiring layers is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines the formation of the oxide insulating layer over the peripheral portion of the oxide semiconductor layer with the existing gate insulating layer formation process. By using the same sputtering conditions and forming the oxide insulating layer simultaneously with the gate insulating layer, the patent achieves increased distance between gate and wiring layers (reducing parasitic capacitance) without adding separate manufacturing steps.
2Productivity
If circuit miniaturization is performed to increase integration density, then integration density is increased, but parasitic capacitance between wirings increases
Solution Approach 1:
The patent applies local quality by forming the oxide insulating layer specifically over the peripheral portion of the oxide semiconductor layer where wiring intersections occur. This localized approach addresses the parasitic capacitance problem at critical intersection points without requiring overall circuit redesign, enabling circuit miniaturization while maintaining low parasitic capacitance at sensitive locations.
3Speed
If signal transmission speed is increased to improve operational speed, then operational speed is improved, but signal distortion increases due to parasitic capacitance
Solution Approach 1:
The patent converts the potentially harmful effect of close wiring proximity (which would increase parasitic capacitance) into a benefit by selectively forming the oxide insulating layer only at peripheral portions and intersections. This allows wirings to be placed close together for high-speed signal transmission while the oxide insulating layer at critical points compensates for the increased parasitic capacitance, maintaining signal integrity.
Data Source
AI summary
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.