Semiconductor Device P-type Assist Layer Overcurrent Tolerance

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Solution Overview

Problem

Power control semiconductor devices face challenges in tolerating overcurrent during the on-state, particularly due to unbalanced charge distribution leading to potential differences and short-circuit breakdowns, especially in the termination region where charge imbalance is not corrected by hole injection.

Innovation Solution

Incorporating a p-type assist layer in the termination region of the semiconductor device, which injects holes into the n-type base layer to balance charges and suppress potential differences, thereby enhancing the device's tolerance to overcurrent and short-circuit conditions, while strategically positioning this layer to minimize impact on breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a power control semiconductor device is designed with conventional structure, then the device can operate normally, but the device has poor tolerance for overcurrent in the on-state due to unbalanced charge distribution

Engineering Contradiction:
Improveovercurrent toleranceVSAvoidcharge imbalance leading to short-circuit breakdown
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A p-type assist layer is introduced as an intermediary component between the n-type base layer and the p-type collector layer. This assist layer acts as a mediator that provides additional hole injection capability to correct charge imbalance in the n-type base layer during overcurrent conditions, thereby preventing short-circuit breakdown without disrupting the normal operation of the device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The p-type assist layer is strategically positioned in specific regions where charge imbalance is most problematic. By locally enhancing hole injection capability in these critical areas, the device achieves improved overcurrent tolerance without compromising the overall breakdown voltage characteristics. The assist layer is placed to optimize its effect on charge balance while minimizing impact on other device parameters.

Inventive Principle:
Principle #3Local quality

2Reliability

If the p-type assist layer is added to improve overcurrent tolerance, then charge balance is improved, but the breakdown voltage may be affected

Engineering Contradiction:
Improveovercurrent toleranceVSAvoidbreakdown voltage
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The impurity concentration of the p-type assist layer is carefully controlled to be lower than that of the p-type collector layer. This parameter optimization ensures that the assist layer provides sufficient hole injection for charge balance correction during overcurrent conditions, while its lower doping level prevents excessive impact on the breakdown voltage characteristics. The specific concentration range is selected to balance these two competing requirements.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The p-type assist layer is positioned at specific locations where it can most effectively correct charge imbalance without interfering with the high-field regions that determine breakdown voltage. By strategically placing the assist layer in areas where charge balance is critical but breakdown field effects are minimal, the design achieves improved overcurrent tolerance while preserving adequate breakdown voltage.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The p-type assist layer effectively improves the semiconductor device's tolerance to overcurrent and short-circuit conditions by balancing charges within the n-type base layer, reducing the risk of short-circuit breakdown and maintaining adequate breakdown voltage, with an optimal width range for effective operation.

Implementation Method 1

the p-type assist layer (23) is provided between the n-type base layer (11) and the collector electrode (20) in the termination region (TR)... which injects holes into the n-type base layer to balance charges

Methodology Applied
Scientific EffectHole injection: Holes

Data Source

PatentUS20230223464A1Semiconductor device
Publication Date: 2023.07.13 KK TOSHIBA
  • US20230223464A1 patent drawing
  • US20230223464A1 patent drawing
  • US20230223464A1 patent drawing

AI summary

A semiconductor device includes a semiconductor part, first and second electrodes and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided between the semiconductor part and the second electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type, and second, fourth, sixth and seventh layers of a second conductivity type. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are provided between the first layer and the first electrode. The sixth layer surrounds the second and third layers. The seventh layer is provided between the first layer and the first electrode. The seventh layer surrounds the fourth and fifth layers and is apart from the fourth and fifth layers.